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magnum88
2022-08-24 08:41:00 +02:00
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h
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/**
******************************************************************************
* @file stm32h7xx_hal.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_H
#define __STM32H7xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_conf.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 0 (VREF_OUT2) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 1 (VREF_OUT1) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 2 (VREF_OUT4) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 3 (VREF_OUT3) */
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
/**
* @}
*/
/** @defgroup SYSCFG_Ethernet_Config Ethernet Config
* @{
*/
#define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */
#define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */
#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \
((CONFIG) == SYSCFG_ETH_RMII))
/**
* @}
*/
/** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config
* @{
*/
#define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */
#define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */
#define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */
#define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */
#define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \
(((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \
(((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \
(((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))
#define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */
#define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */
#define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */
#define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/
#define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */
#define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */
#define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */
#define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */
#define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \
(((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \
(((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))
/**
* @}
*/
/** @defgroup SYSCFG_Boot_Config Boot Config
* @{
*/
#define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */
#define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */
#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \
((REGISTER) == SYSCFG_BOOT_ADDR1))
#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)
/**
* @}
*/
/** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config
* @{
*/
#define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
#define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */
#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \
((SELECT) == SYSCFG_REGISTER_CODE))
#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10))
/**
* @}
*/
/** @defgroup EXTI_Event_Input_Config Event Input Config
* @{
*/
#define EXTI_MODE_IT ((uint32_t)0x00010000)
#define EXTI_MODE_EVT ((uint32_t)0x00020000)
#define EXTI_RISING_EDGE ((uint32_t)0x00100000)
#define EXTI_FALLING_EDGE ((uint32_t)0x00200000)
#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))
#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))
#define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */
#define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */
#define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */
#define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */
#define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */
#define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */
#define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */
#define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */
#define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */
#define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */
#define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */
#define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */
#define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */
#define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */
#define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */
#define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */
#define EXTI_LINE16 ((uint32_t)0x10)
#define EXTI_LINE17 ((uint32_t)0x11)
#define EXTI_LINE18 ((uint32_t)0x12)
#define EXTI_LINE19 ((uint32_t)0x13)
#define EXTI_LINE20 ((uint32_t)0x14)
#define EXTI_LINE21 ((uint32_t)0x15)
#define EXTI_LINE22 ((uint32_t)0x16)
#define EXTI_LINE23 ((uint32_t)0x17)
#define EXTI_LINE24 ((uint32_t)0x18)
#define EXTI_LINE25 ((uint32_t)0x19)
#define EXTI_LINE26 ((uint32_t)0x1A)
#define EXTI_LINE27 ((uint32_t)0x1B)
#define EXTI_LINE28 ((uint32_t)0x1C)
#define EXTI_LINE29 ((uint32_t)0x1D)
#define EXTI_LINE30 ((uint32_t)0x1E)
#define EXTI_LINE31 ((uint32_t)0x1F)
#define EXTI_LINE32 ((uint32_t)0x20)
#define EXTI_LINE33 ((uint32_t)0x21)
#define EXTI_LINE34 ((uint32_t)0x22)
#define EXTI_LINE35 ((uint32_t)0x23)
#define EXTI_LINE36 ((uint32_t)0x24)
#define EXTI_LINE37 ((uint32_t)0x25)
#define EXTI_LINE38 ((uint32_t)0x26)
#define EXTI_LINE39 ((uint32_t)0x27)
#define EXTI_LINE40 ((uint32_t)0x28)
#define EXTI_LINE41 ((uint32_t)0x29)
#define EXTI_LINE42 ((uint32_t)0x2A)
#define EXTI_LINE43 ((uint32_t)0x2B)
#define EXTI_LINE44 ((uint32_t)0x2C)
/* EXTI_LINE45 Reserved */
/* EXTI_LINE46 Reserved */
#define EXTI_LINE47 ((uint32_t)0x2F)
#define EXTI_LINE48 ((uint32_t)0x30)
#define EXTI_LINE49 ((uint32_t)0x31)
#define EXTI_LINE50 ((uint32_t)0x32)
#define EXTI_LINE51 ((uint32_t)0x33)
#define EXTI_LINE52 ((uint32_t)0x34)
#define EXTI_LINE53 ((uint32_t)0x35)
#define EXTI_LINE54 ((uint32_t)0x36)
#define EXTI_LINE55 ((uint32_t)0x37)
#define EXTI_LINE56 ((uint32_t)0x38)
#define EXTI_LINE57 ((uint32_t)0x39)
#define EXTI_LINE58 ((uint32_t)0x3A)
#define EXTI_LINE59 ((uint32_t)0x3B)
#define EXTI_LINE60 ((uint32_t)0x3C)
#define EXTI_LINE61 ((uint32_t)0x3D)
#define EXTI_LINE62 ((uint32_t)0x3E)
#define EXTI_LINE63 ((uint32_t)0x3F)
#define EXTI_LINE64 ((uint32_t)0x40)
#define EXTI_LINE65 ((uint32_t)0x41)
#define EXTI_LINE66 ((uint32_t)0x42)
#define EXTI_LINE67 ((uint32_t)0x43)
#define EXTI_LINE68 ((uint32_t)0x44)
#define EXTI_LINE69 ((uint32_t)0x45)
#define EXTI_LINE70 ((uint32_t)0x46)
#define EXTI_LINE71 ((uint32_t)0x47)
#define EXTI_LINE72 ((uint32_t)0x48)
#define EXTI_LINE73 ((uint32_t)0x49)
#define EXTI_LINE74 ((uint32_t)0x4A)
#define EXTI_LINE75 ((uint32_t)0x4B)
#define EXTI_LINE76 ((uint32_t)0x4C)
/* EXTI_LINE77 Reserved */
/* EXTI_LINE78 Reserved */
/* EXTI_LINE79 Reserved */
/* EXTI_LINE80 Reserved */
/* EXTI_LINE81 Reserved */
/* EXTI_LINE82 Reserved */
/* EXTI_LINE83 Reserved */
/* EXTI_LINE84 Reserved */
#define EXTI_LINE85 ((uint32_t)0x55)
#define EXTI_LINE86 ((uint32_t)0x56)
#define EXTI_LINE87 ((uint32_t)0x57)
/* EXTI_LINE88 Reserved */
#define IS_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
((LINE) == EXTI_LINE44) || \
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \
((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \
((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \
((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \
((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \
((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \
((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \
((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \
((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \
((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \
((LINE) == EXTI_LINE44) || \
((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \
((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \
((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \
((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \
((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \
((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \
((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \
((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \
((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \
((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \
((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
((LINE) == EXTI_LINE85) || \
((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \
((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \
((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \
((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \
((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
((LINE) == EXTI_LINE53))
#define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/
#define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/
#define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/
#define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/
#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \
((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
/**
* @}
*/
/** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config
* @{
*/
#define FMC_SWAPBMAP_DISABLE (0x00000000U)
#define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0
#define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1
#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \
((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \
((__MODE__) == FMC_SWAPBMAP_SDRAMB2))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))
#define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))
#define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))
#define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))
#define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))
#define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))
#define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))
#define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))
#define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))
#define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))
#define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))
#define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))
#define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))
#define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))
#define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))
#define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))
#define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))
#define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))
#define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))
#define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))
#define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))
#define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))
#define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))
#define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))
#define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))
#define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))
#define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))
#define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))
#define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))
#define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))
#define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))
#define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))
#define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))
#define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))
#define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))
#define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))
#define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))
#define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))
#define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))
#define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))
#define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))
#define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))
#define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))
#define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))
#define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))
#define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))
#define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))
#define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))
#define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC))
#define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(__IO uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
void HAL_SYSCFG_EnableBOOST(void);
void HAL_SYSCFG_DisableBOOST(void);
void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_SYSCFG_EnableIOSpeedOptimize(void);
void HAL_SYSCFG_DisableIOSpeedOptimize(void);
void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
void HAL_EnableDBGSleepMode(void);
void HAL_DisableDBGSleepMode(void);
void HAL_EnableDBGStopMode(void);
void HAL_DisableDBGStopMode(void);
void HAL_EnableDBGStandbyMode(void);
void HAL_DisableDBGStandbyMode(void);
void HAL_EnableDomain3DBGStopMode(void);
void HAL_DisableDomain3DBGStopMode(void);
void HAL_EnableDomain3DBGStandbyMode(void);
void HAL_DisableDomain3DBGStandbyMode(void);
void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );
void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);
void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd);
void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);
void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);
uint32_t HAL_GetFMCMemorySwappingConfig(void);
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h
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/**
******************************************************************************
* @file stm32h7xx_hal_adc.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_ADC_H
#define __STM32H7xx_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief ADC Regular Conversion Oversampling structure definition
*/
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio. */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADCEx_Right_Bit_Shift */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
This parameter can be a value of @ref ADCEx_Triggered_Oversampling_Mode */
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
The oversampling is either temporary stopped or reset upon an injected
sequence interruption.
If oversampling is enabled on both regular and injected groups, this parameter
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
(the oversampling buffer is zeroed during injection sequence).
This parameter can be a value of @ref ADCEx_Regular_Oversampling_Mode */
}ADC_OversamplingTypeDef;
/**
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from System/PLL2/PLL3 clocks) and clock prescaler.
This parameter can be a value of @ref ADC_ClockPrescaler.
Note: The clock is common for all the ADCs.
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 16, 14, 12 or 10 bits,
AHB clock frequency /3 for resolution 8 bits.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of the ADC dedicated PLL clock, it must be preliminarily enabled at RCC top level.
Note: This parameter can be modified only if all ADCs are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_Resolution */
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
Scan direction is upward: from rank 1 to rank 'n'.
This parameter can be a value of @ref ADC_Scan_mode */
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag
to free the IRQ vector sequencer.
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16.
Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
continuous mode or external trigger that could launch a conversion). */
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
This parameter can be a value of @ref ADC_ConversionDataManagement.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups
(ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter applies to ADC group regular only.
This parameter can be a value of @ref ADC_Overrun.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
uint32_t LeftBitShift; /*!< Configures the left shifting applied to the final result with or without oversampling.
This parameter can be a value of @ref ADCEx_Left_Bit_Shift */
FunctionalState BoostMode; /*!< Configures the Boost mode control.
When selecting an analog ADC clock frequency bigger than 20MHz,
it is mandatory to first enable the BOOST Mode.
This parameter can be set to ENABLE or DISABLE. */
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
}ADC_InitTypeDef;
/**
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
* ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
*/
typedef struct
{
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
This parameter can be a value of @ref ADCEx_analog_watchdog_number. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel/all channels, ADC groups regular and/or injected.
For Analog Watchdog 2 and 3: There is no configuration for all channels as AWD1. Set value 'ADC_ANALOGWATCHDOG_NONE' to reset
channels group programmed with parameter 'Channel', set any other value to program the channel(s) to be monitored.
This parameter can be a value of @ref ADCEx_analog_watchdog_mode. */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
This parameter can be a value of @ref ADC_channels. */
FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (16, 14, 12, 10 or 8 bits), this parameter must be a number
between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
Depending of ADC resolution selected (16, 14, 12, or 8 bits), this parameter must be a number
between Min_Data = 0x0000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively. */
}ADC_AnalogWDGConfTypeDef;
/** @defgroup ADC_States ADC States
* @{
*/
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
#define HAL_ADC_ERROR_JQOVF ((uint32_t)0x08) /*!< Injected context queue overflow error */
/**
* @}
*/
/** @defgroup ADC_ClockPrescaler ADC clock source and clock prescaler
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CCR_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_CKMODE) /*!< ADC synchronous clock derived from AHB clock divided by 4 */
#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */
#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /*!< ADC asynchronous clock not divided */
#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0) /*!< ADC asynchronous clock divided by 2 */
#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1) /*!< ADC asynchronous clock divided by 4 */
#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 6 */
#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)(ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock divided by 8 */
#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 10 */
#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 12 */
#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_2|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 16 */
#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)(ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock divided by 32 */
#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 64 */
#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock divided by 128 */
#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_3|ADC_CCR_PRESC_1|ADC_CCR_PRESC_0)) /*!< ADC asynchronous clock divided by 256 */
/**
* @}
*/
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_16B ((uint32_t)0x00000000) /*!< ADC 16-bit resolution */
#define ADC_RESOLUTION_14B ((uint32_t)ADC_CFGR_RES_0) /*!< ADC 14-bit resolution */
#define ADC_RESOLUTION_12B ((uint32_t)ADC_CFGR_RES_1) /*!< ADC 12-bit resolution */
#define ADC_RESOLUTION_10B ((uint32_t)(ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) /*!< ADC 10-bit resolution */
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR_RES_2) /*!< ADC 8-bit resolution */
/**
* @}
*/
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
#define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
#define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
/**
* @}
*/
/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
* @{
*/
/* External triggers of regular group for ADC1, ADC2, ADC3 */
#define ADC_EXTERNALTRIG_T1_CC1 ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIG_T1_CC2 ((uint32_t)ADC_CFGR_EXTSEL_0)
#define ADC_EXTERNALTRIG_T1_CC3 ((uint32_t)ADC_CFGR_EXTSEL_1)
#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)(ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)ADC_CFGR_EXTSEL_2)
#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define ADC_EXTERNALTRIG_T8_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_T8_TRGO2 ((uint32_t) ADC_CFGR_EXTSEL_3)
#define ADC_EXTERNALTRIG_T1_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_T1_TRGO2 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1))
#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2))
#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_T15_TRGO ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1))
#define ADC_EXTERNALTRIG_T3_CC4 ((uint32_t)(ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_HR1_ADCTRG1 ((uint32_t) ADC_CFGR_EXTSEL_4)
#define ADC_EXTERNALTRIG_HR1_ADCTRG3 ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_LPTIM1_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1))
#define ADC_EXTERNALTRIG_LPTIM2_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0))
#define ADC_EXTERNALTRIG_LPTIM3_OUT ((uint32_t) (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2))
#define ADC_SOFTWARE_START ((uint32_t)0x00000001)
/**
* @}
*/
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) /*!< Regular conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
* @{
*/
#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) /*!< End of unitary conversion flag */
#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) /*!< End of sequence conversions flag */
/**
* @}
*/
/** @defgroup ADC_Overrun ADC overrun
* @{
*/
#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) /*!< Data preserved in case of overrun */
#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR_OVRMOD) /*!< Data overwritten in case of overrun */
/**
* @}
*/
/** @defgroup ADC_regular_rank ADC group regular sequencer rank
* @{
*/
#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
/**
* @}
*/
/** @defgroup ADC_channels ADC Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)(0x00000000))
#define ADC_CHANNEL_1 ((uint32_t)(ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_2 ((uint32_t)(ADC_SQR3_SQ10_1))
#define ADC_CHANNEL_3 ((uint32_t)(ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_4 ((uint32_t)(ADC_SQR3_SQ10_2))
#define ADC_CHANNEL_5 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_6 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define ADC_CHANNEL_7 ((uint32_t)(ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_8 ((uint32_t)(ADC_SQR3_SQ10_3))
#define ADC_CHANNEL_9 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_10 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1))
#define ADC_CHANNEL_11 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_12 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2))
#define ADC_CHANNEL_13 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_14 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1))
#define ADC_CHANNEL_15 ((uint32_t)(ADC_SQR3_SQ10_3 | ADC_SQR3_SQ10_2 | ADC_SQR3_SQ10_1 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR3_SQ10_4))
#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_0))
#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1))
#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR3_SQ10_4 | ADC_SQR3_SQ10_1| ADC_SQR3_SQ10_0))
/* Note: Vbat/4, TempSensor and VREFINT internal channels are available on ADC3 only */
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_17
#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
#define ADC_CHANNEL_VREFINT ADC_CHANNEL_19
/* Note: DAC1CH1 and DAC1CH2 internal channels is available on ADC2 only */
#define ADC_CHANNEL_DAC1CH1_ADC2 (ADC_CHANNEL_16) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
#define ADC_CHANNEL_DAC1CH2_ADC2 (ADC_CHANNEL_17) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
/**
* @}
*/
/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
* @{
*/
#define ADC_CONVERSIONDATA_DR ((uint32_t)0x00000000) /*!< Regular Conversion data stored in DR register only */
#define ADC_CONVERSIONDATA_DFSDM ((uint32_t)ADC_CFGR_DMNGT_1) /*!< DFSDM mode selected */
#define ADC_CONVERSIONDATA_DMA_ONESHOT ((uint32_t)ADC_CFGR_DMNGT_0) /*!< DMA one shot mode selected */
#define ADC_CONVERSIONDATA_DMA_CIRCULAR ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ADC_Private_Macro ADC Private Macros
* @{
*/
/**
* @brief Verify the ADC data conversion setting.
* @param DATA : programmed DATA conversion mode.
* @retval SET (DATA is a valid value) or RESET (DATA is invalid)
*/
#define IS_ADC_CONVERSIONDATAMGT(DATA) \
((((DATA) == ADC_CONVERSIONDATA_DR)) || \
(((DATA) == ADC_CONVERSIONDATA_DFSDM)) || \
(((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \
(((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))
/**
* @brief Test if conversion trigger of regular group is software start
* or external trigger.
* @param __HANDLE__: ADC handle
* @retval SET (software start) or RESET (external trigger)
*/
#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
(((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET)
/**
* @brief Returns resolution bits in CFGR register: RES[1:0].
* Returned value is among parameters in @ref ADC_Resolution.
* @param __HANDLE__: ADC handle
* @retval Parameter of @ref ADC_Resolution set.
*/
#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
/**
* @brief Clear ADC error code (set it to error code: "no error")
* @param __HANDLE__: ADC handle
* @retval None
*/
#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/**
* @brief Verification of ADC state: enabled or disabled
* @param __HANDLE__: ADC handle
* @retval SET (ADC enabled) or RESET (ADC disabled)
*/
#define ADC_IS_ENABLE(__HANDLE__) \
(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
) ? SET : RESET)
/**
* @brief Check if no conversion on going on regular group
* @param __HANDLE__: ADC handle
* @retval SET (conversion is on going) or RESET (no conversion is on going)
*/
#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
) ? RESET : SET)
/**
* @brief Simultaneously clears and sets specific bits of the handle State
* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
* the first parameter is the ADC handle State, the second parameter is the
* bit field to clear, the third and last parameter is the bit field to set
* @retval None
*/
#define ADC_STATE_CLR_SET MODIFY_REG
/**
* @brief Verify that a given value is aligned with the ADC resolution range.
* @param RESOLUTION: ADC resolution (16, 14, 12, 10 or 8 bits).
* @param ADC_VALUE: value checked against the resolution.
* @retval SET (ADC_VALUE in line with RESOLUTION) or RESET (ADC_VALUE not in line with RESOLUTION)
*/
#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
((((RESOLUTION) == ADC_RESOLUTION_16B) && ((ADC_VALUE) <= ((uint32_t)0xFFFF))) || \
(((RESOLUTION) == ADC_RESOLUTION_14B) && ((ADC_VALUE) <= ((uint32_t)0x3FFF))) || \
(((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \
(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \
(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))))
/**
* @brief Verify the length of the scheduled regular conversions group.
* @param LENGTH: number of programmed conversions.
* @retval SET (LENGTH is within the maximum number of possible programmable regular conversions) or RESET (LENGTH is null or too large)
*/
#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
/**
* @brief Verify the number of scheduled regular conversions in discontinuous mode.
* @param NUMBER: number of scheduled regular conversions in discontinuous mode.
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large)
*/
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
/**
* @brief Verify the ADC clock setting.
* @param ADC_CLOCK : programmed ADC clock.
* @retval SET (ADC_CLOCK is a valid value) or RESET (ADC_CLOCK is invalid)
*/
#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128) || \
((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256) )
/**
* @brief Verify the ADC resolution setting.
* @param RESOLUTION: programmed ADC resolution.
* @retval SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)
*/
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_16B) || \
((RESOLUTION) == ADC_RESOLUTION_14B) || \
((RESOLUTION) == ADC_RESOLUTION_12B) || \
((RESOLUTION) == ADC_RESOLUTION_10B) || \
((RESOLUTION) == ADC_RESOLUTION_8B) )
/**
* @brief Verify the ADC resolution setting when limited to 8 bits.
* @param RESOLUTION: programmed ADC resolution when limited to 8 bits.
* @retval SET (RESOLUTION is a valid value) or RESET (RESOLUTION is invalid)
*/
#define IS_ADC_RESOLUTION_8_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B))
/**
* @brief Verify the ADC scan mode.
* @param SCAN_MODE: programmed ADC scan mode.
* @retval SET (SCAN_MODE is valid) or RESET (SCAN_MODE is invalid)
*/
#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
((SCAN_MODE) == ADC_SCAN_ENABLE) )
/**
* @brief Verify the ADC edge trigger setting for regular group.
* @param EDGE: programmed ADC edge trigger setting.
* @retval SET (EDGE is a valid value) or RESET (EDGE is invalid)
*/
#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
/**
* @brief Verify the ADC regular conversions external trigger.
* @param REGTRIG: programmed ADC regular conversions external trigger.
* @retval SET (REGTRIG is a valid value) or RESET (REGTRIG is invalid)
*/
#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_CC1) || \
((REGTRIG) == ADC_EXTERNALTRIG_T1_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIG_T1_CC3) || \
((REGTRIG) == ADC_EXTERNALTRIG_T2_CC2) || \
((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIG_T4_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIG_T4_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIG_T6_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIG_T15_TRGO) || \
((REGTRIG) == ADC_EXTERNALTRIG_T3_CC4) || \
((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG1) || \
((REGTRIG) == ADC_EXTERNALTRIG_HR1_ADCTRG3) || \
((REGTRIG) == ADC_EXTERNALTRIG_LPTIM1_OUT) || \
((REGTRIG) == ADC_EXTERNALTRIG_LPTIM2_OUT) || \
((REGTRIG) == ADC_EXTERNALTRIG_LPTIM3_OUT) || \
((REGTRIG) == ADC_SOFTWARE_START) )
/**
* @brief Verify the ADC regular conversions check for converted data availability.
* @param EOC_SELECTION: converted data availability check.
* @retval SET (EOC_SELECTION is a valid value) or RESET (EOC_SELECTION is invalid)
*/
#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \
((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
/**
* @brief Verify the ADC regular conversions overrun handling.
* @param OVR: ADC regular conversions overrun handling.
* @retval SET (OVR is a valid value) or RESET (OVR is invalid)
*/
#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \
((OVR) == ADC_OVR_DATA_OVERWRITTEN) )
/**
* @brief Verify the ADC conversions sampling time.
* @param TIME: ADC conversions sampling time.
* @retval SET (TIME is a valid value) or RESET (TIME is invalid)
*/
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \
((TIME) == ADC_SAMPLETIME_2CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_8CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_16CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_32CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_64CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_387CYCLES_5) || \
((TIME) == ADC_SAMPLETIME_810CYCLES_5) )
/**
* @brief Verify the ADC regular channel setting.
* @param __CHANNEL__: programmed ADC regular channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
((__CHANNEL__) == ADC_REGULAR_RANK_16) )
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup ADC_Private_Constants ADC Private Constants
* @{
*/
/* Fixed timeout values for ADC conversion (including sampling time) */
/* Maximum sampling time is 810.5 ADC clock cycle */
/* Maximum conversion time is 16.5 + Maximum sampling time */
/* or 16.5 + 810.5 = 827 ADC clock cycles */
/* Minimum ADC Clock frequency is 0.35 MHz */
/* Maximum conversion time is */
/* 827 / 0.35 MHz = 2.36 ms */
#define ADC_STOP_CONVERSION_TIMEOUT ((uint32_t) 5)
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 120)
/* Delay for ADC voltage regulator startup time */
/* Maximum delay is 10 microseconds */
/* (refer device RM, parameter Tadcvreg_stup). */
#define ADC_STAB_DELAY_US ((uint32_t) 10) /*!< ADC voltage regulator startup time */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup ADC_Exported_Macro ADC Exported Macros
* @{
*/
/**
* @brief Reset ADC handle state
* @param __HANDLE__: ADC handle
* @retval None
*/
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
/**
* @brief Checks if the specified ADC interrupt source is enabled or disabled.
* @param __HANDLE__: ADC handle
* @param __INTERRUPT__: ADC interrupt source to check
* This parameter can be one of the following values:
* @arg ADC_IT_RDY ADC Ready (ADRDY) interrupt source
* @arg ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg ADC_IT_OVR ADC overrun interrupt source
* @arg ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
* @retval State of interruption (SET or RESET)
*/
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(( ((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__) \
)? SET : RESET \
)
/**
* @brief Enable an ADC interrupt.
* @param __HANDLE__: ADC handle
* @param __INTERRUPT__: ADC Interrupt to enable
* This parameter can be one of the following values:
* @arg ADC_IT_RDY ADC Ready (ADRDY) interrupt source
* @arg ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg ADC_IT_OVR ADC overrun interrupt source
* @arg ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
* @retval None
*/
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable an ADC interrupt.
* @param __HANDLE__: ADC handle
* @param __INTERRUPT__: ADC Interrupt to disable
* @arg ADC_IT_RDY ADC Ready (ADRDY) interrupt source
* @arg ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg ADC_IT_OVR ADC overrun interrupt source
* @arg ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source
* @retval None
*/
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified ADC flag is set or not.
* @param __HANDLE__: ADC handle
* @param __FLAG__: ADC flag to check
* This parameter can be one of the following values:
* @arg ADC_FLAG_RDY ADC Ready (ADRDY) flag
* @arg ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg ADC_FLAG_OVR ADC overrun flag
* @arg ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear a specified ADC flag
* @param __HANDLE__: ADC handle
* @param __FLAG__: ADC flag to clear
* This parameter can be one of the following values:
* @arg ADC_FLAG_RDY ADC Ready (ADRDY) flag
* @arg ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg ADC_FLAG_OVR ADC overrun flag
* @arg ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag
* @note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR)
* @retval None
*/
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR) = (__FLAG__))
/**
* @}
*/
/* Include ADC HAL Extended module */
#include "stm32h7xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions ADC Exported Functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group1 Initialization and deinitialization functions
* @brief ADC Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group2 Input and Output operation functions
* @brief ADC IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
/* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
/**
* @}
*/
/* Peripheral State functions *************************************************/
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/* Private functions -----------------------------------------------------------*/
/** @addtogroup ADC_Private_Functions ADC Private Functions
* @{
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32H7xx_ADC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_cec.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CEC_H
#define __STM32H7xx_HAL_CEC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup CEC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CEC_Exported_Types CEC Exported Types
* @{
*/
/**
* @brief CEC Init Structure definition
*/
typedef struct
{
uint32_t SignalFreeTime; /*!< Set SFT field, specifies the Signal Free Time.
It can be one of @ref CEC_Signal_Free_Time
and belongs to the set {0,...,7} where
0x0 is the default configuration
else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */
uint32_t Tolerance; /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,
it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE
or CEC_EXTENDED_TOLERANCE */
uint32_t BRERxStop; /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.
- CEC_NO_RX_STOP_ON_BRE: reception is not stopped.
- CEC_RX_STOP_ON_BRE: reception is stopped. */
uint32_t BREErrorBitGen; /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Bit Rising Error detection.
- CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.
- CEC_BRE_ERRORBIT_GENERATION: error-bit generation if BRESTP is set. */
uint32_t LBPEErrorBitGen; /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the
CEC line upon Long Bit Period Error detection.
- CEC_LBPE_ERRORBIT_NO_GENERATION: no error-bit generation.
- CEC_LBPE_ERRORBIT_GENERATION: error-bit generation. */
uint32_t BroadcastMsgNoErrorBitGen; /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line
upon an error detected on a broadcast message.
It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:
- CEC_BROADCASTERROR_ERRORBIT_GENERATION.
- a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE
and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.
- b) LBPE detection: error-bit generation on the CEC line
if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.
- CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.
no error-bit generation in case neither a) nor b) are satisfied. Additionally,
there is no error-bit generation in case of Short Bit Period Error detection in
a broadcast message while LSTN bit is set. */
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
- CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
- CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
- CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its
own address (OAR). Messages addressed to different destination are ignored.
Broadcast messages are always received.
- CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own
address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */
}CEC_InitTypeDef;
/**
* @brief HAL CEC State structures definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
}HAL_CEC_StateTypeDef;
/**
* @brief CEC handle Structure definition
*/
typedef struct
{
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
}CEC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CEC_Exported_Constants CEC Exported Constants
* @{
*/
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
#define HAL_CEC_ERROR_LBPE CEC_ISR_LBPE /*!< CEC Rx Long Bit period Error */
#define HAL_CEC_ERROR_RXACKE CEC_ISR_RXACKE /*!< CEC Rx Missing Acknowledge */
#define HAL_CEC_ERROR_ARBLST CEC_ISR_ARBLST /*!< CEC Arbitration Lost */
#define HAL_CEC_ERROR_TXUDR CEC_ISR_TXUDR /*!< CEC Tx-Buffer Underrun */
#define HAL_CEC_ERROR_TXERR CEC_ISR_TXERR /*!< CEC Tx-Error */
#define HAL_CEC_ERROR_TXACKE CEC_ISR_TXACKE /*!< CEC Tx Missing Acknowledge */
/**
* @}
*/
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
/**
* @}
*/
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
*/
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
*/
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
*/
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
*/
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
*/
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
*/
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
*/
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
/**
* @}
*/
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
/**
* @}
*/
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
/**
* @}
*/
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
* @{
*/
#define CEC_IT_TXACKE CEC_IER_TXACKEIE
#define CEC_IT_TXERR CEC_IER_TXERRIE
#define CEC_IT_TXUDR CEC_IER_TXUDRIE
#define CEC_IT_TXEND CEC_IER_TXENDIE
#define CEC_IT_TXBR CEC_IER_TXBRIE
#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
#define CEC_IT_RXACKE CEC_IER_RXACKEIE
#define CEC_IT_LBPE CEC_IER_LBPEIE
#define CEC_IT_SBPE CEC_IER_SBPEIE
#define CEC_IT_BRE CEC_IER_BREIE
#define CEC_IT_RXOVR CEC_IER_RXOVRIE
#define CEC_IT_RXEND CEC_IER_RXENDIE
#define CEC_IT_RXBR CEC_IER_RXBRIE
/**
* @}
*/
/** @defgroup CEC_Flags_Definitions CEC Flags definition
* @{
*/
#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
#define CEC_FLAG_TXERR CEC_ISR_TXERR
#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
#define CEC_FLAG_TXEND CEC_ISR_TXEND
#define CEC_FLAG_TXBR CEC_ISR_TXBR
#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
#define CEC_FLAG_LBPE CEC_ISR_LBPE
#define CEC_FLAG_SBPE CEC_ISR_SBPE
#define CEC_FLAG_BRE CEC_ISR_BRE
#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
#define CEC_FLAG_RXEND CEC_ISR_RXEND
#define CEC_FLAG_RXBR CEC_ISR_RXBR
/**
* @}
*/
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags
* @{
*/
#define CEC_ISR_ALL_ERROR ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\
CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag
* @{
*/
#define CEC_IER_RX_ALL_ERR ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)
/**
* @}
*/
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag
* @{
*/
#define CEC_IER_TX_ALL_ERR ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CEC_Exported_Macros CEC Exported Macros
* @{
*/
/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__: CEC handle.
* @retval None
*/
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
} while(0)
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__: specifies the CEC Handle.
* @param __FLAG__: specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval ITStatus
*/
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1)
* @param __HANDLE__: specifies the CEC Handle.
* @param __FLAG__: specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
* @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
* @arg CEC_FLAG_TXBR: Tx-Byte Request.
* @arg CEC_FLAG_ARBLST: Arbitration Lost
* @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
* @arg CEC_FLAG_LBPE: Rx Long period Error
* @arg CEC_FLAG_SBPE: Rx Short period Error
* @arg CEC_FLAG_BRE: Rx Bit Rising Error
* @arg CEC_FLAG_RXOVR: Rx Overrun.
* @arg CEC_FLAG_RXEND: End Of Reception.
* @arg CEC_FLAG_RXBR: Rx-Byte Received.
* @retval none
*/
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval none
*/
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
* @param __HANDLE__: specifies the CEC Handle.
* @param __INTERRUPT__: specifies the CEC interrupt to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
* @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable
* @arg CEC_IT_TXEND: End of transmission IT Enable
* @arg CEC_IT_TXBR: Tx-Byte Request IT Enable
* @arg CEC_IT_ARBLST: Arbitration Lost IT Enable
* @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable
* @arg CEC_IT_LBPE: Rx Long period Error IT Enable
* @arg CEC_IT_SBPE: Rx Short period Error IT Enable
* @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable
* @arg CEC_IT_RXOVR: Rx Overrun IT Enable
* @arg CEC_IT_RXEND: End Of Reception IT Enable
* @arg CEC_IT_RXBR: Rx-Byte Received IT Enable
* @retval FlagStatus
*/
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag
* @param __HANDLE__: specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag
* @param __HANDLE__: specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register
* @param __HANDLE__: specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
* @param __HANDLE__: specifies the CEC Handle.
* @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CEC_Exported_Functions
* @{
*/
/** @addtogroup CEC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/** @addtogroup CEC_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CEC_Private_Types CEC Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CEC_Private_Variables CEC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CEC_Private_Macros CEC Private Macros
* @{
*/
#define IS_CEC_SIGNALFREETIME(__SFT__) ((__SFT__) <= CEC_CFGR_SFT)
#define IS_CEC_TOLERANCE(__RXTOL__) (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \
((__RXTOL__) == CEC_EXTENDED_TOLERANCE))
#define IS_CEC_BRERXSTOP(__BRERXSTOP__) (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \
((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \
((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \
((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))
#define IS_CEC_SFTOP(__SFTOP__) (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \
((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
((__MODE__) == CEC_FULL_LISTENING_MODE))
/** @brief Check CEC message size.
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header).
* @param __SIZE__: CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__: CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__: CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_CEC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h
+807
View File
@@ -0,0 +1,807 @@
/**
******************************************************************************
* @file stm32h7xx_hal_comp.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_COMP_H
#define __STM32H7xx_HAL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances
(2 consecutive instances odd and even COMP<x> and COMP<x+1>).
Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.
This parameter can be a value of @ref COMP_WindowMode */
uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed.
Note: For the characteritics of comparator power modes
(propagation delay and power consumption), refer to device datasheet.
This parameter can be a value of @ref COMP_PowerMode */
uint32_t NonInvertingInput; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_InputPlus */
uint32_t InvertingInput; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_InputMinus */
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_Hysteresis */
uint32_t OutputPol; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_OutputPolarity */
uint32_t BlankingSrce; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_BlankingSrce */
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
}COMP_InitTypeDef;
/**
* @brief HAL COMP state machine: HAL COMP states definition
*/
#define COMP_STATE_BITFIELD_LOCK ((uint32_t)0x10)
typedef enum
{
HAL_COMP_STATE_RESET = 0x00, /*!< COMP not yet initialized */
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
HAL_COMP_STATE_READY = 0x01, /*!< COMP initialized and ready for use */
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
}HAL_COMP_StateTypeDef;
/**
* @brief COMP Handle Structure definition
*/
typedef struct
{
COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
} COMP_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_WindowMode COMP Window Mode
* @{
*/
#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */
#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */
/**
* @}
*/
/** @defgroup COMP_PowerMode COMP power mode
* @{
*/
/* Note: For the characteritics of comparator power modes */
/* (propagation delay and power consumption), */
/* refer to device datasheet. */
#define COMP_POWERMODE_HIGHSPEED ((uint32_t)0x00000000) /*!< High Speed */
#define COMP_POWERMODE_MEDIUMSPEED (COMP_CFGRx_PWRMODE_0) /*!< Medium Speed */
#define COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE) /*!< Ultra-low power mode */
/**
* @}
*/
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
* @{
*/
#define COMP_INPUT_PLUS_IO1 ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */
#define COMP_INPUT_PLUS_IO2 (COMP_CFGRx_INPSEL) /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */
/**
* @}
*/
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
* @{
*/
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CFGRx_INMSEL_2 ) /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_0) /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
#define COMP_INPUT_MINUS_IO1 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
#define COMP_INPUT_MINUS_IO2 (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
/**
* @}
*/
/** @defgroup COMP_Hysteresis COMP hysteresis
* @{
*/
#define COMP_HYSTERESIS_NONE ((uint32_t)0x00000000) /*!< No hysteresis */
#define COMP_HYSTERESIS_LOW (COMP_CFGRx_HYST_0) /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM (COMP_CFGRx_HYST_1) /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH (COMP_CFGRx_HYST) /*!< Hysteresis level high */
/**
* @}
*/
/** @defgroup COMP_OutputPolarity COMP Output Polarity
* @{
*/
#define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_INVERTED (COMP_CFGRx_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
/**
* @}
*/
/** @defgroup COMP_BlankingSrce COMP Blanking Source
* @{
*/
/* Any blanking source can be selected for all comparators */
#define COMP_BLANKINGSRC_NONE ((uint32_t)0x00000000) /*!< No blanking source */
#define COMP_BLANKINGSRC_TIM1_OC5 (COMP_CFGRx_BLANKING_0) /*!< TIM1 OC5 selected as blanking source for comparator */
#define COMP_BLANKINGSRC_TIM2_OC3 (COMP_CFGRx_BLANKING_1) /*!< TIM2 OC3 selected as blanking source for comparator */
#define COMP_BLANKINGSRC_TIM3_OC3 (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1) /*!< TIM3 OC3 selected as blanking source for compartor */
#define COMP_BLANKINGSRC_TIM3_OC4 (COMP_CFGRx_BLANKING_2) /*!< TIM3 OC4 selected as blanking source for comparator */
#define COMP_BLANKINGSRC_TIM8_OC5 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0) /*!< TIM8 OC5 selected as blanking source for comparator */
#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1) /*!< TIM15 OC1 selected as blanking source for comparator */
/**
* @}
*/
/** @defgroup COMP_OutputLevel COMP Output Level
* @{
*/
/* Note: Comparator output level values are fixed to "0" and "1", */
/* corresponding COMP register bit is managed by HAL function to match */
/* with these values (independently of bit position in register). */
/* When output polarity is not inverted, comparator output is low when
the input plus is at a lower voltage than the input minus */
#define COMP_OUTPUT_LEVEL_LOW ((uint32_t)0x00000000)
/* When output polarity is not inverted, comparator output is high when
the input plus is at a higher voltage than the input minus */
#define COMP_OUTPUT_LEVEL_HIGH ((uint32_t)0x00000001)
/**
* @}
*/
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
* @{
*/
#define COMP_TRIGGERMODE_NONE ((uint32_t)0x00000000) /*!< Comparator output triggering no External Interrupt Line */
#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
/**
* @}
*/
/** @defgroup COMP_Flag COMP Flag
* @{
*/
#define COMP_FLAG_C1I COMP_SR_C1IF /*!< Comparator 1 Interrupt Flag */
#define COMP_FLAG_C2I COMP_SR_C2IF /*!< Comparator 2 Interrupt Flag */
#define COMP_FLAG_LOCK COMP_CFGRx_LOCK /*!< Lock flag */
/**
* @}
*/
/** @defgroup COMP_IT_CLEAR_Flags COMP Interruption Clear Flags
* @{
*/
#define COMP_CLEAR_C1IF COMP_ICFR_C1IF /*!< Clear Comparator 1 Interrupt Flag */
#define COMP_CLEAR_C2IF COMP_ICFR_C2IF /*!< Clear Comparator 2 Interrupt Flag */
/**
* @}
*/
/** @defgroup COMP_Interrupts_Definitions COMP Interrupts Definitions
* @{
*/
#define COMP_IT_EN COMP_CFGRx_ITEN
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup COMP_Exported_Macros COMP Exported Macros
* @{
*/
/** @defgroup COMP_Handle_Management COMP Handle Management
* @{
*/
/** @brief Reset COMP handle state.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
/**
* @brief Enable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
/**
* @brief Disable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)
/**
* @brief Lock the specified comparator configuration.
* @note Using this macro induce HAL COMP handle state machine being no
* more in line with COMP instance state.
* To keep HAL COMP handle state machine updated, it is recommended
* to use function "HAL_COMP_Lock')".
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)
/**
* @brief Check whether the specified comparator is locked.
* @param __HANDLE__ COMP handle
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
*/
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)
/**
* @}
*/
/** @defgroup COMP_Exti_Management COMP external interrupt line management
* @{
*/
/**
* @brief Enable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Enable the COMP1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Check whether the COMP1 EXTI line flag is set or not.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Clear the COMP1 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Generate a software interrupt on the COMP1 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 D3 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 D3 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Enable the COMP2 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Check whether the COMP2 EXTI line flag is set or not.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Clear the the COMP2 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 D3 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT() SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 D3 EXTI Line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT() CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)
/**
* @brief Generate a software interrupt on the COMP2 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)
/** @brief Checks if the specified COMP interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the COMP Handle.
* This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.
* @param __INTERRUPT__: specifies the COMP interrupt source to check.
* This parameter can be one of the following values:
* @arg COMP_IT_EN: Comparator interrupt enable
*
* @retval The new state of __IT__ (TRUE or FALSE)
*/
#define __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified COMP flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg COMP_FLAG_C1I: Comparator 1 Interrupt Flag
* @arg COMP_FLAG_C2I: Comparator 2 Interrupt Flag
* @retval The new state of __FLAG__ (TRUE or FALSE)
*/
#define __HAL_COMP_GET_FLAG(__FLAG__) ((COMP12->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified COMP pending flag.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg COMP_CLEAR_C1IF : Clear Comparator 1 Interrupt Flag
* @arg COMP_CLEAR_C2IF : Clear Comparator 2 Interrupt Flag
* @retval None
*/
#define __HAL_COMP_CLEAR_FLAG(__FLAG__) (COMP12->ICFR = (__FLAG__))
/** @brief Clear the COMP C1I flag.
* @retval None
*/
#define __HAL_COMP_CLEAR_C1IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)
/** @brief Clear the COMP C2I flag.
* @retval None
*/
#define __HAL_COMP_CLEAR_C2IFLAG() __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)
/** @brief Enable the specified COMP interrupt.
* @param __HANDLE__: specifies the COMP Handle.
* @param __INTERRUPT__: specifies the COMP interrupt source to enable.
* This parameter can be one of the following values:
* @arg COMP_CFGRx_ITEN : Comparator interrupt
* @retval None
*/
#define __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )
/** @brief Disable the specified COMP interrupt.
* @param __HANDLE__: specifies the COMP Handle.
* @param __INTERRUPT__: specifies the COMP interrupt source to enable.
* This parameter can be one of the following values:
* @arg COMP_CFGRx_ITEN : Comparator interrupt
* @retval None
*/
#define __HAL_COMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))
/**
* @}
*/
/** @brief Enable the specified bit in the Option register.
* @param __AF__: specifies the Alternate Function source selection .
* This parameter can be one of the following values:
* @arg COMP_OR_AFOPA6 : Alternate Function PA6 source selection
* @arg COMP_OR_AFOPA8 : Alternate Function PA8 source selection
* @arg COMP_OR_AFOPB12 : Alternate Function PB12 source selection
* @arg COMP_OR_AFOPE6 : Alternate Function PE6 source selection
* @arg COMP_OR_AFOPE15 : Alternate Function PE15 source selection
* @arg COMP_OR_AFOPG2 : Alternate Function PG2 source selection
* @arg COMP_OR_AFOPG3 : Alternate Function PG3 source selection
* @arg COMP_OR_AFOPG4 : Alternate Function PG4 source selection
* @arg COMP_OR_AFOPI1 : Alternate Function PI1 source selection
* @arg COMP_OR_AFOPI4 : Alternate Function PI4 source selection
* @arg COMP_OR_AFOPK2 : Alternate Function PK2 source selection
* @retval None
*/
#define __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))
/** @brief Disable the specified bit in the Option register.
* @param __AF__: specifies the Alternate Function source selection .
* This parameter can be one of the following values:
* @arg COMP_OR_AFOPA6 : Alternate Function PA6 source selection
* @arg COMP_OR_AFOPA8 : Alternate Function PA8 source selection
* @arg COMP_OR_AFOPB12 : Alternate Function PB12 source selection
* @arg COMP_OR_AFOPE6 : Alternate Function PE6 source selection
* @arg COMP_OR_AFOPE15 : Alternate Function PE15 source selection
* @arg COMP_OR_AFOPG2 : Alternate Function PG2 source selection
* @arg COMP_OR_AFOPG3 : Alternate Function PG3 source selection
* @arg COMP_OR_AFOPG4 : Alternate Function PG4 source selection
* @arg COMP_OR_AFOPI1 : Alternate Function PI1 source selection
* @arg COMP_OR_AFOPI4 : Alternate Function PI4 source selection
* @arg COMP_OR_AFOPK2 : Alternate Function PK2 source selection
* @retval None
*/
#define __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup COMP_Private_Constants COMP Private Constants
* @{
*/
/** @defgroup COMP_ExtiLine COMP EXTI Lines
* @{
*/
#define COMP_EXTI_LINE_COMP1 (EXTI_IMR1_IM20) /*!< EXTI line 20 connected to COMP1 output */
#define COMP_EXTI_LINE_COMP2 (EXTI_IMR1_IM21) /*!< EXTI line 21 connected to COMP2 output */
/**
* @}
*/
/** @defgroup COMP_ExtiLine COMP EXTI Lines
* @{
*/
#define COMP_EXTI_IT ((uint32_t) 0x01) /*!< EXTI line event with interruption */
#define COMP_EXTI_EVENT ((uint32_t) 0x02) /*!< EXTI line event only (without interruption) */
#define COMP_EXTI_RISING ((uint32_t) 0x10) /*!< EXTI line event on rising edge */
#define COMP_EXTI_FALLING ((uint32_t) 0x20) /*!< EXTI line event on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_Private_Macros COMP Private Macros
* @{
*/
/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators
* @{
*/
/**
* @brief Get the specified EXTI line for a comparator instance.
* @param __INSTANCE__: specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
COMP_EXTI_LINE_COMP2)
/**
* @}
*/
/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters
* @{
*/
#define IS_COMP_WINDOWMODE(__WINDOWMODE__) (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE) || \
((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON) )
#define IS_COMP_POWERMODE(__POWERMODE__) (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED) || \
((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER) )
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
((__POL__) == COMP_OUTPUTPOL_INVERTED))
#define IS_COMP_BLANKINGSRCE(__SOURCE__) (((__SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5) || \
((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup COMP_Exported_Functions
* @{
*/
/** @addtogroup COMP_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup COMP_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup COMP_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
/* Callback in Interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral State functions **************************************************/
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_COMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h
+434
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@@ -0,0 +1,434 @@
/**
******************************************************************************
* @file stm32h7xx_hal_conf_template.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32h7xx_hal_conf.h.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CONF_H
#define __STM32H7xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_CEC_MODULE_ENABLED
#define HAL_COMP_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DCMI_MODULE_ENABLED
#define HAL_DFSDM_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_DMA2D_MODULE_ENABLED
#define HAL_ETH_MODULE_ENABLED
#define HAL_FDCAN_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_HASH_MODULE_ENABLED
#define HAL_HCD_MODULE_ENABLED
#define HAL_HRTIM_MODULE_ENABLED
#define HAL_HSEM_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_JPEG_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
#define HAL_LTDC_MODULE_ENABLED
#define HAL_MDIOS_MODULE_ENABLED
#define HAL_MDMA_MODULE_ENABLED
#define HAL_MMC_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_OPAMP_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_QSPI_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_SDRAM_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SMBUS_MODULE_ENABLED
#define HAL_SPDIFRX_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_SWPMI_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal oscillator (CSI) default value.
* This value is the default CSI value after Reset.
*/
#if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S peripheral
* This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the External clock in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0x0F) /*!< tick interrupt priority */
#define USE_RTOS 0
#define USE_SD_TRANSCEIVER 1U /*!< use uSD Transceiver */
/* ########################### Ethernet Configuration ######################### */
#define ETH_TX_DESC_CNT 4 /* number of Ethernet Tx DMA descriptors */
#define ETH_RX_DESC_CNT 4 /* number of Ethernet Rx DMA descriptors */
#define ETH_MAC_ADDR0 ((uint8_t)0x02)
#define ETH_MAC_ADDR1 ((uint8_t)0x00)
#define ETH_MAC_ADDR2 ((uint8_t)0x00)
#define ETH_MAC_ADDR3 ((uint8_t)0x00)
#define ETH_MAC_ADDR4 ((uint8_t)0x00)
#define ETH_MAC_ADDR5 ((uint8_t)0x00)
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1 */
/* ################## SPI peripheral configuration ########################## */
/**
* @brief Used to activate CRC feature inside HAL SPI Driver
* Activated (1U): CRC code is compiled within HAL SPI driver
* Deactivated (0U): CRC code excluded from HAL SPI driver
*/
#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32h7xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32h7xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32h7xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_HASH_MODULE_ENABLED
#include "stm32h7xx_hal_hash.h"
#endif /* HAL_HASH_MODULE_ENABLED */
#ifdef HAL_DCMI_MODULE_ENABLED
#include "stm32h7xx_hal_dcmi.h"
#endif /* HAL_DCMI_MODULE_ENABLED */
#ifdef HAL_DMA2D_MODULE_ENABLED
#include "stm32h7xx_hal_dma2d.h"
#endif /* HAL_DMA2D_MODULE_ENABLED */
#ifdef HAL_DFSDM_MODULE_ENABLED
#include "stm32h7xx_hal_dfsdm.h"
#endif /* HAL_DFSDM_MODULE_ENABLED */
#ifdef HAL_ETH_MODULE_ENABLED
#include "stm32h7xx_hal_eth.h"
#endif /* HAL_ETH_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32h7xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32h7xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
#include "stm32h7xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32h7xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32h7xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32h7xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32h7xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32h7xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32h7xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32h7xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
#ifdef HAL_HSEM_MODULE_ENABLED
#include "stm32h7xx_hal_hsem.h"
#endif /* HAL_HSEM_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32h7xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32h7xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32h7xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32h7xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32h7xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32h7xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_JPEG_MODULE_ENABLED
#include "stm32h7xx_hal_jpeg.h"
#endif /* HAL_JPEG_MODULE_ENABLED */
#ifdef HAL_MDIOS_MODULE_ENABLED
#include "stm32h7xx_hal_mdios.h"
#endif /* HAL_MDIOS_MODULE_ENABLED */
#ifdef HAL_MDMA_MODULE_ENABLED
#include "stm32h7xx_hal_mdma.h"
#endif /* HAL_MDMA_MODULE_ENABLED */
#ifdef HAL_MMC_MODULE_ENABLED
#include "stm32h7xx_hal_mmc.h"
#endif /* HAL_MMC_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32h7xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_LTDC_MODULE_ENABLED
#include "stm32h7xx_hal_ltdc.h"
#endif /* HAL_LTDC_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32h7xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32h7xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32h7xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32h7xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32h7xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32h7xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SD_MODULE_ENABLED
#include "stm32h7xx_hal_sd.h"
#endif /* HAL_SD_MODULE_ENABLED */
#ifdef HAL_SDRAM_MODULE_ENABLED
#include "stm32h7xx_hal_sdram.h"
#endif /* HAL_SDRAM_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32h7xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SPDIFRX_MODULE_ENABLED
#include "stm32h7xx_hal_spdifrx.h"
#endif /* HAL_SPDIFRX_MODULE_ENABLED */
#ifdef HAL_SWPMI_MODULE_ENABLED
#include "stm32h7xx_hal_swpmi.h"
#endif /* HAL_SWPMI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32h7xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32h7xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32h7xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32h7xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32h7xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32h7xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32h7xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32h7xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_HCD_MODULE_ENABLED
#include "stm32h7xx_hal_hcd.h"
#endif /* HAL_HCD_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t* file, uint32_t line);
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cortex.h
+489
View File
@@ -0,0 +1,489 @@
/**
******************************************************************************
* @file stm32h7xx_hal_cortex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CORTEX_H
#define __STM32H7xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup CORTEX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types Cortex Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported Macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/**
* @}
*/
/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier
* @{
*/
#define CM7_CPUID (uint32_t)0x00000003
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CORTEX_Exported_Functions
* @{
*/
/** @addtogroup CORTEX_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @addtogroup CORTEX_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
#if (__MPU_PRESENT == 1)
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
uint32_t HAL_GetCurrentCPUID(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CORTEX_Private_Functions CORTEX Private Functions
* @brief CORTEX private functions
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Disables the MPU
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Disable(void)
{
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU */
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/**
* @brief Enables the MPU
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
}
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_CORTEX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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+423
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/**
******************************************************************************
* @file stm32h7xx_hal_crc.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CRC_H
#define __STM32H7xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup CRC CRC
* @brief CRC HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/** @defgroup CRC_Exported_Types_Group1 CRC State Structure definition
* @{
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
}HAL_CRC_StateTypeDef;
/**
* @}
*/
/** @defgroup CRC_Exported_Types_Group2 CRC Init Structure definition
* @{
*/
typedef struct
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field.
If otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial. 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal representation,
e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.
No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
CRC_POLYLENGTH_32B (32-bit CRC)
CRC_POLYLENGTH_16B (16-bit CRC)
CRC_POLYLENGTH_8B (8-bit CRC)
CRC_POLYLENGTH_7B (7-bit CRC) */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
is set to DEFAULT_INIT_VALUE_ENABLE */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
CRC_INPUTDATA_INVERSION_NONE no input data inversion
CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2
CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C
CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or
CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */
}CRC_InitTypeDef;
/**
* @}
*/
/** @defgroup CRC_Exported_Types_Group3 CRC Handle Structure definition
* @{
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data)
CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of half-words (16-bit data)
CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words (32-bits data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error
must occur if InputBufferFormat is not one of the three values listed above */
}CRC_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC exported constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7U
/**
* @}
*/
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
/**
* @}
*/
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
/**
* @}
*/
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
/**
* @}
*/
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
* @{
*/
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
/**
* @}
*/
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32U
#define HAL_CRC_LENGTH_16B 16U
#define HAL_CRC_LENGTH_8B 8U
#define HAL_CRC_LENGTH_7B 7U
/**
* @}
*/
/** @defgroup CRC_Input_Buffer_Format CRC input buffer format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC exported macros
* @{
*/
/** @brief Reset CRC handle state
* @param __HANDLE__: CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__: CRC handle
* @retval None.
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ : CRC handle
* @param __INIT__ : 32-bit initial value
* @retval None.
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
* @brief Stores a 32-bit data in the Independent Data(ID) register.
* @param __HANDLE__: CRC handle
* @param __VALUE__: 32-bit value to be stored in the ID register
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Returns the 32-bit data stored in the Independent Data(ID) register.
* @param __HANDLE__: CRC handle
* @retval 32-bit value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Include CRC HAL Extension module */
#include "stm32h7xx_hal_crc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Aliases for inter STM32 series compatibility */
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CRC_Private_Types CRC Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRC_Private_Defines CRC Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRC_Private_Variables CRC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRC_Private_Constants CRC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \
((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \
((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE))
#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \
((__LENGTH__) == CRC_POLYLENGTH_16B) || \
((__LENGTH__) == CRC_POLYLENGTH_8B) || \
((__LENGTH__) == CRC_POLYLENGTH_7B))
#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \
((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup CRC_Private_Functions_Prototypes CRC Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRC_Private_Functions CRC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_CRC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc_ex.h
+168
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/**
******************************************************************************
* @file stm32h7xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CRC_EX_H
#define __STM32H7xx_HAL_CRC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup CRCEx CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants
* @{
*/
/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \
((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \
((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((__MODE__) == CRC_INPUTDATA_INVERSION_WORD))
/**
* @}
*/
/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros
* @{
*/
/**
* @brief Set CRC output reversal
* @param __HANDLE__ : CRC handle
* @retval None.
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ : CRC handle
* @retval None.
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ : CRC handle
* @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
* @retval None.
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
/**
* @}
*/
/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions
* @{
*/
/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions
* @{
*/
/* Exported functions --------------------------------------------------------*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
/* Peripheral Control functions ***********************************************/
/* Peripheral State and Error functions ***************************************/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_CRC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h
+466
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/**
******************************************************************************
* @file stm32h7xx_hal_cryp.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CRYP_H
#define __STM32H7xx_HAL_CRYP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (CRYP)
/** @addtogroup CRYP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRYP_Exported_Types CRYP Exported Types
* @{
*/
/**
* @brief CRYP Init Structure definition
*/
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
This parameter can be a value of @ref CRYP_Key_Size */
uint32_t* pKey; /*!< The key used for encryption/decryption */
uint32_t* pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
AES Algorithm ECB/CBC/CTR/GCM or CCM
This parameter can be a value of @ref CRYP_Algorithm_Mode */
uint32_t* Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer in word */
uint32_t* B0; /*!< B0 is first authentication block used only in AES CCM mode */
}CRYP_ConfigTypeDef;
/**
* @brief CRYP State Structure definition
*/
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U /*!< CRYP BUSY, internal processing is ongoing */
}HAL_CRYP_STATETypeDef;
/**
* @brief CRYP handle Structure definition
*/
typedef struct
{
CRYP_TypeDef *Instance; /*!< CRYP registers base address */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
__IO uint16_t CrypHeaderCount; /*!< Counter of header data */
__IO uint16_t CrypInCount; /*!< Counter of input data */
__IO uint16_t CrypOutCount; /*!< Counter of output data */
uint16_t Size; /*!< length of input data in word */
uint32_t Phase; /*!< CRYP peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
HAL_LockTypeDef Lock; /*!< CRYP locking object */
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
}CRYP_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
* @{
*/
/** @defgroup CRYP_Error_Definition CRYP Error Definition
* @{
*/
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
/**
* @}
*/
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
#define CRYP_DES_ECB CRYP_CR_ALGOMODE_DES_ECB
#define CRYP_DES_CBC CRYP_CR_ALGOMODE_DES_CBC
#define CRYP_TDES_ECB CRYP_CR_ALGOMODE_TDES_ECB
#define CRYP_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC
#define CRYP_AES_ECB CRYP_CR_ALGOMODE_AES_ECB
#define CRYP_AES_CBC CRYP_CR_ALGOMODE_AES_CBC
#define CRYP_AES_CTR CRYP_CR_ALGOMODE_AES_CTR
#define CRYP_AES_GCM CRYP_CR_ALGOMODE_AES_GCM
#define CRYP_AES_CCM CRYP_CR_ALGOMODE_AES_CCM
/**
* @}
*/
/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
#define CRYP_KEYSIZE_128B 0x00000000U
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
/**
* @}
*/
/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
#define CRYP_DATATYPE_32B 0x00000000U
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
/**
* @}
*/
/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
#define CRYP_IT_INI CRYP_IMSCR_INIM /*!< Input FIFO Interrupt */
#define CRYP_IT_OUTI CRYP_IMSCR_OUTIM /*!< Output FIFO Interrupt */
/**
* @}
*/
/** @defgroup CRYP_Flags CRYP Flags
* @{
*/
/* Flags in the SR register */
#define CRYP_FLAG_IFEM CRYP_SR_IFEM /*!< Input FIFO is empty */
#define CRYP_FLAG_IFNF CRYP_SR_IFNF /*!< Input FIFO is not Full */
#define CRYP_FLAG_OFNE CRYP_SR_OFNE /*!< Output FIFO is not empty */
#define CRYP_FLAG_OFFU CRYP_SR_OFFU /*!< Output FIFO is Full */
#define CRYP_FLAG_BUSY CRYP_SR_BUSY /*!< The CRYP core is currently processing a block of data
or a key preparation (for AES decryption). */
/* Flags in the RISR register */
#define CRYP_FLAG_OUTRIS 0x01000002U /*!< Output FIFO service raw interrupt status */
#define CRYP_FLAG_INRIS 0x01000001U /*!< Input FIFO service raw interrupt status*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
* @{
*/
/**
* @brief Enable/Disable the CRYP peripheral.
* @param __HANDLE__: specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CRYP_CR_CRYPEN)
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values for CRYP:
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
* or a key preparation (for AES decryption).
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: specifies the interrupt to check.
* This parameter can be one of the following values for CRYP:
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Enable the CRYP interrupt.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP Interrupt.
* This parameter can be one of the following values for CRYP:
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
* @retval None
*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
* @param __HANDLE__: specifies the CRYP handle.
* @param __INTERRUPT__: CRYP Interrupt.
* This parameter can be one of the following values for CRYP:
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
* @retval None
*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
/**
* @}
*/
/* Include CRYP HAL Extended module */
#include "stm32h7xx_hal_cryp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
*/
/** @addtogroup CRYP_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf );
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group2
* @{
*/
/* encryption/decryption ***********************************/
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group3
* @{
*/
/* Interrupt Handler functions **********************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRYP_Private_Macros CRYP Private Macros
* @{
*/
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
* @{
*/
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB) || \
((ALGORITHM) == CRYP_DES_CBC) || \
((ALGORITHM) == CRYP_TDES_ECB) || \
((ALGORITHM) == CRYP_TDES_CBC) || \
((ALGORITHM) == CRYP_AES_ECB) || \
((ALGORITHM) == CRYP_AES_CBC) || \
((ALGORITHM) == CRYP_AES_CTR) || \
((ALGORITHM) == CRYP_AES_GCM) || \
((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
((KEYSIZE) == CRYP_KEYSIZE_192B) || \
((KEYSIZE) == CRYP_KEYSIZE_256B))
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
((DATATYPE) == CRYP_DATATYPE_16B) || \
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Constants CRYP Private Constants
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Functions CRYP Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
#endif /* CRYP */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_CRYP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp_ex.h
+141
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/**
******************************************************************************
* @file stm32h7xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_CRYP_EX_H
#define __STM32H7xx_HAL_CRYP_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (CRYP)
/** @addtogroup CRYPEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
* @{
*/
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* CRYP */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_CRYP_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h
+480
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/**
******************************************************************************
* @file stm32h7xx_hal_dac.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DAC_H
#define __STM32H7xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
}HAL_DAC_StateTypeDef;
/**
* @brief DAC handle Structure definition
*/
typedef struct
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
}DAC_HandleTypeDef;
/**
* @brief DAC Configuration sample and hold Channel structure definition
*/
typedef struct
{
uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
}
DAC_SampleAndHoldConfTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
This parameter can be a value of @ref DAC_SampleAndHold */
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection */
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref DAC_UserTrimming
DAC_UserTrimming is either factory or user trimming */
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
}DAC_ChannelConfTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
#define HAL_DAC_ERROR_TIMEOUT 0x08 /*!< Timeout error */
/**
* @}
*/
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T5_TRGO ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T6_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T8_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TEN1)) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HR1_TRGO1 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HR1_TRGO2 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LP1_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< LP1 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_LP2_OUT ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< LP2 OUT TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
/**
* @}
*/
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_MCR_MODE1_1)
/**
* @}
*/
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
* @{
*/
#define DAC_CHIPCONNECT_DISABLE ((uint32_t)0x00000000)
#define DAC_CHIPCONNECT_ENABLE ((uint32_t)DAC_MCR_MODE1_0)
/**
* @}
*/
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
#define DAC_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
#define DAC_TRIMMING_USER ((uint32_t)0x00000001) /*!< User trimming */
/**
* @}
*/
/** @defgroup DAC_SampleAndHold. Mode is Sample and hold (low power or normal)
* @{
*/
#define DAC_SAMPLEANDHOLD_DISABLE ((uint32_t)0x00000000)
#define DAC_SAMPLEANDHOLD_ENABLE ((uint32_t)DAC_MCR_MODE1_2)
/**
* @}
*/
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
/**
* @}
*/
/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_IT_definition DAC IT definition
* @{
*/
#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
/** @brief Reset DAC handle state.
* @param __HANDLE__: specifies the DAC handle.
* @retval None
*/
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
/** @brief Enable the DAC channel.
* @param __HANDLE__: specifies the DAC handle.
* @param __DAC_Channel__: specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Disable the DAC channel.
* @param __HANDLE__: specifies the DAC handle
* @param __DAC_Channel__: specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Set DHR12R1 alignment.
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment.
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment.
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt.
* @param __HANDLE__: specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt.
* @param __HANDLE__: specifies the DAC handle
* @param __INTERRUPT__: specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not.
* @param __HANDLE__: DAC handle
* @param __INTERRUPT__: DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__: specifies the DAC handle.
* @param __FLAG__: specifies the DAC flag to get.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__: specifies the DAC handle.
* @param __FLAG__: specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FF)
/**
* @}
*/
/* Include DAC HAL Extended module */
#include "stm32h7xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32H7xx_HAL_DAC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h
+248
View File
@@ -0,0 +1,248 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dac_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DAC_EX_H
#define __STM32H7xx_HAL_DAC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL State structures definition
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS4_0 ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS5_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS6_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS7_0 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS8_0 ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
#define DAC_TRIANGLEAMPLITUDE_31 ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
#define DAC_TRIANGLEAMPLITUDE_63 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
#define DAC_TRIANGLEAMPLITUDE_127 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
#define DAC_TRIANGLEAMPLITUDE_255 ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
#define DAC_TRIANGLEAMPLITUDE_511 ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
#define DAC_TRIANGLEAMPLITUDE_1023 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIANGLEAMPLITUDE_2047 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HR1_TRGO1) || \
((TRIGGER) == DAC_TRIGGER_HR1_TRGO2) || \
((TRIGGER) == DAC_TRIGGER_LP1_OUT) || \
((TRIGGER) == DAC_TRIGGER_LP2_OUT) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FF)
#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FF)
#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
((CONNECT) == DAC_CHIPCONNECT_ENABLE))
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
((TRIMMING) == DAC_TRIMMING_USER))
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Extended features functions ***********************************************/
/** @addtogroup DACEx_Exported_Functions
* @{
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
/**
* @}
*/
/** @addtogroup DACEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DACEx_Private_Functions
* @{
*/
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
/* are called by HAL_DAC_Start_DMA */
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__STM32H7xx_HAL_DAC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h
+624
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@@ -0,0 +1,624 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DCMI_H
#define __STM32H7xx_HAL_DCMI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DCMI DCMI
* @brief DCMI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DCMI_Exported_Types DCMI Exported Types
* @{
*/
/**
* @brief HAL DCMI State structures definition
*/
typedef enum
{
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
}HAL_DCMI_StateTypeDef;
/**
* @brief DCMI Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
}DCMI_CodesInitTypeDef;
/**
* @brief DCMI Init structure definition
*/
typedef struct
{
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
This parameter can be a value of @ref DCMI_Synchronization_Mode */
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
This parameter can be a value of @ref DCMI_Capture_Rate */
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
line/frame end delimiter */
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_MODE_JPEG */
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
This parameter can be a value of @ref DCMI_Byte_Select_Mode */
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Byte_Select_Start */
uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
This parameter can be a value of @ref DCMI_Line_Select_Mode */
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Line_Select_Start */
}DCMI_InitTypeDef;
/**
* @brief DCMI handle Structure definition
*/
typedef struct
{
DCMI_TypeDef *Instance; /*!< DCMI Register base address */
DCMI_InitTypeDef Init; /*!< DCMI parameters */
HAL_LockTypeDef Lock; /*!< DCMI locking object */
__IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
__IO uint32_t XferCount; /*!< DMA transfer counter */
__IO uint32_t XferSize; /*!< DMA transfer size */
uint32_t XferTransferNumber; /*!< DMA transfer number */
uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
__IO uint32_t ErrorCode; /*!< DCMI Error code */
}DCMI_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DCMI_Exported_Constants DCMI Exported Constants
* @{
*/
/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
#define HAL_DCMI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_DCMI_ERROR_OVR (0x00000001U) /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC (0x00000002U) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA (0x00000040U) /*!< DMA error */
/**
* @}
*/
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS (0x00000000U) /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */
/**
* @}
*/
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{
*/
#define DCMI_SYNCHRO_HARDWARE (0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
/**
* @}
*/
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
* @{
*/
#define DCMI_PCKPOLARITY_FALLING (0x00000000U) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
/**
* @}
*/
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
* @{
*/
#define DCMI_VSPOLARITY_LOW (0x00000000U) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
/**
* @}
*/
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW (0x00000000U) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
/**
* @}
*/
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
* @{
*/
#define DCMI_JPEG_DISABLE (0x00000000U) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
/**
* @}
*/
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
* @{
*/
#define DCMI_CR_ALL_FRAME (0x00000000U) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
/**
* @}
*/
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
* @{
*/
#define DCMI_EXTEND_DATA_8B (0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
/**
* @}
*/
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{
*/
#define DCMI_WINDOW_COORDINATE (0x3FFFU) /*!< Window coordinate */
/**
* @}
*/
/** @defgroup DCMI_Window_Height DCMI Window Height
* @{
*/
#define DCMI_WINDOW_HEIGHT (0x1FFFU) /*!< Window Height */
/**
* @}
*/
/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
* @{
*/
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
/**
* @}
*/
/** @defgroup DCMI_Flags DCMI Flags
* @{
*/
/**
* @brief DCMI SR register
*/
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
/**
* @brief DCMI RIS register
*/
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
/**
* @brief DCMI MIS register
*/
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
/**
* @}
*/
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
* @{
*/
#define DCMI_BSM_ALL (0x00000000U) /*!< Interface captures all received data */
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
/**
* @}
*/
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
* @{
*/
#define DCMI_OEBS_ODD (0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
/**
* @}
*/
/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
* @{
*/
#define DCMI_LSM_ALL (0x00000000U) /*!< Interface captures all received lines */
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
/**
* @}
*/
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
* @{
*/
#define DCMI_OELS_ODD (0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DCMI_Exported_Macros DCMI Exported Macros
* @{
*/
/** @brief Reset DCMI handle state
* @param __HANDLE__: specifies the DCMI handle.
* @retval None
*/
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
/**
* @brief Enable the DCMI.
* @param __HANDLE__: DCMI handle
* @retval None
*/
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
/**
* @brief Disable the DCMI.
* @param __HANDLE__: DCMI handle
* @retval None
*/
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
/* Interrupt & Flag management */
/**
* @brief Get the DCMI pending flag.
* @param __HANDLE__: DCMI handle
* @param __FLAG__: Get the specified flag.
* This parameter can be one of the following values (no combination allowed)
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
* @arg DCMI_FLAG_FNE: FIFO empty flag
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
* @arg DCMI_FLAG_LINERI: Line flag mask
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
* @retval The state of FLAG.
*/
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
(((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
/**
* @brief Clear the DCMI pending flags.
* @param __HANDLE__: DCMI handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
* @arg DCMI_FLAG_OVFRI: Overflow flag mask
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
* @arg DCMI_FLAG_LINERI: Line flag mask
* @retval None
*/
#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified DCMI interrupts.
* @param __HANDLE__: DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
* @arg DCMI_IT_LINE: Line interrupt mask
* @retval None
*/
#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disable the specified DCMI interrupts.
* @param __HANDLE__: DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
* @arg DCMI_IT_LINE: Line interrupt mask
* @retval None
*/
#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DCMI interrupt has occurred or not.
* @param __HANDLE__: DCMI handle
* @param __INTERRUPT__: specifies the DCMI interrupt source to check.
* This parameter can be one of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVF: Overflow interrupt mask
* @arg DCMI_IT_ERR: Synchronization error interrupt mask
* @arg DCMI_IT_VSYNC: VSYNC interrupt mask
* @arg DCMI_IT_LINE: Line interrupt mask
* @retval The state of INTERRUPT.
*/
#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
* @{
*/
/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
/**
* @}
*/
/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
/**
* @}
*/
/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
/**
* @}
*/
/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Constants DCMI Private Constants
* @{
*/
#define DCMI_MIS_INDEX (0x1000) /*!< DCMI MIS register index */
#define DCMI_SR_INDEX (0x2000) /*!< DCMI SR register index */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DCMI_Private_Macros DCMI Private Macros
* @{
*/
#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
((MODE) == DCMI_MODE_SNAPSHOT))
#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
((MODE) == DCMI_SYNCHRO_EMBEDDED))
#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
((POLARITY) == DCMI_PCKPOLARITY_RISING))
#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
((POLARITY) == DCMI_VSPOLARITY_HIGH))
#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
((POLARITY) == DCMI_HSPOLARITY_HIGH))
#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
((JPEG_MODE) == DCMI_JPEG_ENABLE))
#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
((DATA) == DCMI_EXTEND_DATA_10B) || \
((DATA) == DCMI_EXTEND_DATA_12B) || \
((DATA) == DCMI_EXTEND_DATA_14B))
#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
((MODE) == DCMI_BSM_OTHER) || \
((MODE) == DCMI_BSM_ALTERNATE_4) || \
((MODE) == DCMI_BSM_ALTERNATE_2))
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
((POLARITY) == DCMI_OEBS_EVEN))
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
((MODE) == DCMI_LSM_ALTERNATE_2))
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
((POLARITY) == DCMI_OELS_EVEN))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_DCMI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_def.h
+208
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/**
******************************************************************************
* @file stm32h7xx_hal_def.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DEF
#define __STM32H7xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx.h"
#include "Legacy/stm32_hal_legacy.h"
#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
#ifndef NULL
#define NULL (void *) 0
#endif
#define HAL_MAX_DELAY 0xFFFFFFFF
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
#if defined (__GNUC__) /* GNU Compiler */
#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
#elif defined (__ICCARM__) /* IAR Compiler */
#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
#elif defined (__CC_ARM) /* ARM Compiler */
#define ALIGN_32BYTES(buf) __align(32) buf
#endif
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
/* ARM Compiler
------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC HAL_StatusTypeDef
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#endif
#ifdef __cplusplus
}
#endif
#endif /* ___STM32H7xx_HAL_DEF */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h
+716
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/**
******************************************************************************
* @file stm32h7xx_hal_dfsdm.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of DFSDM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DFSDM_H
#define __STM32H7xx_HAL_DFSDM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DFSDM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
* @{
*/
/**
* @brief HAL DFSDM Channel states definition
*/
typedef enum
{
HAL_DFSDM_CHANNEL_STATE_RESET = 0x00, /*!< DFSDM channel not initialized */
HAL_DFSDM_CHANNEL_STATE_READY = 0x01, /*!< DFSDM channel initialized and ready for use */
HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFF /*!< DFSDM channel state error */
}HAL_DFSDM_Channel_StateTypeDef;
/**
* @brief DFSDM channel output clock structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Output clock enable/disable */
uint32_t Selection; /*!< Output clock is system clock or audio clock.
This parameter can be a value of @ref DFSDM_Channel_OuputClock */
uint32_t Divider; /*!< Output clock divider.
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
}DFSDM_Channel_OutputClockTypeDef;
/**
* @brief DFSDM channel input structure definition
*/
typedef struct
{
uint32_t Multiplexer; /*!< Input is external serial inputs ,internal register or ADC output.
This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
This parameter can be a value of @ref DFSDM_Channel_DataPacking */
uint32_t Pins; /*!< Input pins are taken from same or following channel.
This parameter can be a value of @ref DFSDM_Channel_InputPins */
}DFSDM_Channel_InputTypeDef;
/**
* @brief DFSDM channel serial interface structure definition
*/
typedef struct
{
uint32_t Type; /*!< SPI or Manchester modes.
This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
This parameter can be a value of @ref DFSDM_Channel_SpiClock */
}DFSDM_Channel_SerialInterfaceTypeDef;
/**
* @brief DFSDM channel analog watchdog structure definition
*/
typedef struct
{
uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}DFSDM_Channel_AwdTypeDef;
/**
* @brief DFSDM channel init structure definition
*/
typedef struct
{
DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
int32_t Offset; /*!< DFSDM channel offset.
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
}DFSDM_Channel_InitTypeDef;
/**
* @brief DFSDM channel handle structure definition
*/
typedef struct
{
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
}DFSDM_Channel_HandleTypeDef;
/**
* @brief HAL DFSDM Filter states definition
*/
typedef enum
{
HAL_DFSDM_FILTER_STATE_RESET = 0x00, /*!< DFSDM filter not initialized */
HAL_DFSDM_FILTER_STATE_READY = 0x01, /*!< DFSDM filter initialized and ready for use */
HAL_DFSDM_FILTER_STATE_REG = 0x02, /*!< DFSDM filter regular conversion in progress */
HAL_DFSDM_FILTER_STATE_INJ = 0x03, /*!< DFSDM filter injected conversion in progress */
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04, /*!< DFSDM filter regular and injected conversions in progress */
HAL_DFSDM_FILTER_STATE_ERROR = 0xFF /*!< DFSDM filter state error */
}HAL_DFSDM_Filter_StateTypeDef;
/**
* @brief DFSDM filter regular conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
This parameter can be a value of @ref DFSDM_Filter_Trigger */
FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
}DFSDM_Filter_RegularParamTypeDef;
/**
* @brief DFSDM filter injected conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
This parameter can be a value of @ref DFSDM_Filter_Trigger */
FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
uint32_t ExtTrigger; /*!< External trigger.
This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
}DFSDM_Filter_InjectedParamTypeDef;
/**
* @brief DFSDM filter parameters structure definition
*/
typedef struct
{
uint32_t SincOrder; /*!< Sinc filter order.
This parameter can be a value of @ref DFSDM_Filter_SincOrder */
uint32_t Oversampling; /*!< Filter oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
uint32_t IntOversampling; /*!< Integrator oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
}DFSDM_Filter_FilterParamTypeDef;
/**
* @brief DFSDM filter init structure definition
*/
typedef struct
{
DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
}DFSDM_Filter_InitTypeDef;
/**
* @brief DFSDM filter handle structure definition
*/
typedef struct
{
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
uint32_t RegularContMode; /*!< Regular conversion continuous mode */
uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
FunctionalState InjectedScanMode; /*!< Injected scanning mode */
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
uint32_t ErrorCode; /*!< DFSDM filter error code */
}DFSDM_Filter_HandleTypeDef;
/**
* @brief DFSDM filter analog watchdog parameters structure definition
*/
typedef struct
{
uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
uint32_t Channel; /*!< Analog watchdog channel selection.
This parameter can be a values combination of @ref DFSDM_Channel_Selection */
int32_t HighThreshold; /*!< High threshold for the analog watchdog.
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
This parameter can be a values combination of @ref DFSDM_BreakSignals */
uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
This parameter can be a values combination of @ref DFSDM_BreakSignals */
}DFSDM_Filter_AwdParamTypeDef;
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
* @{
*/
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
* @{
*/
#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000) /*!< Source for ouput clock is system clock */
#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
/**
* @}
*/
/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
* @{
*/
#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000) /*!< Data are taken from external inputs */
#define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */
#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
/**
* @}
*/
/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
* @{
*/
#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000) /*!< Standard data packing mode */
#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
/**
* @}
*/
/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
* @{
*/
#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000) /*!< Input from pins on same channel */
#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
/**
* @}
*/
/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
* @{
*/
#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000) /*!< SPI with rising edge */
#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
/**
* @}
*/
/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
* @{
*/
#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000) /*!< External SPI clock */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
/**
* @}
*/
/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
* @{
*/
#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */
#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
/**
* @}
*/
/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
* @{
*/
#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000) /*!< Software trigger */
#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001) /*!< Synchronous with DFSDM0 */
#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002) /*!< External trigger (only for injected conversion) */
/**
* @}
*/
/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
* @{
*/
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1 and 2 */
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM 0, 1 and 2 */
#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0 and 1 */
#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_LPTIM1 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0) /*!< For DFSDM 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM 0, 1, 2 and 3 */
/**
* @}
*/
/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
* @{
*/
#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
/**
* @}
*/
/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
* @{
*/
#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000) /*!< FastSinc filter type */
#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
/**
* @}
*/
/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
* @{
*/
#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000) /*!< From digital filter */
#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
/**
* @}
*/
/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
* @{
*/
#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001) /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002) /*!< Overrun occurs during injected conversion */
#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003) /*!< DMA error occurs */
/**
* @}
*/
/** @defgroup DFSDM_BreakSignals DFSDM break signals
* @{
*/
#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000) /*!< No break signal */
#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001) /*!< Break signal 0 */
#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002) /*!< Break signal 1 */
#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004) /*!< Break signal 2 */
#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008) /*!< Break signal 3 */
/**
* @}
*/
/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
* @{
*/
/* DFSDM Channels ------------------------------------------------------------*/
/* The DFSDM channels are defined as follows:
- in 16-bit LSB the channel mask is set
- in 16-bit MSB the channel number is set
e.g. for channel 5 definition:
- the channel mask is 0x00000020 (bit 5 is set)
- the channel number 5 is 0x00050000
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001)
#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002)
#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004)
#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008)
#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010)
#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020)
#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040)
#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080)
/**
* @}
*/
/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
* @{
*/
#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000) /*!< Conversion are not continuous */
#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001) /*!< Conversion are continuous */
/**
* @}
*/
/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
* @{
*/
#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000) /*!< Analog watchdog high threshold */
#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001) /*!< Analog watchdog low threshold */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
* @{
*/
/** @brief Reset DFSDM channel handle state.
* @param __HANDLE__: DFSDM channel handle.
* @retval None
*/
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
/** @brief Reset DFSDM filter handle state.
* @param __HANDLE__: DFSDM filter handle.
* @retval None
*/
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
/**
* @}
*/
/* End of exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
* @{
*/
/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
* @{
*/
/* Channel initialization and de-initialization functions *********************/
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
* @{
*/
/* Channel operation functions ************************************************/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
/**
* @}
*/
/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
* @{
*/
/* Channel state function *****************************************************/
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
* @{
*/
/* Filter initialization and de-initialization functions *********************/
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
* @{
*/
/* Filter control functions *********************/
HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel,
uint32_t ContinuousMode);
HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
* @{
*/
/* Filter operation functions *********************/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
DFSDM_Filter_AwdParamTypeDef* awdParam);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
/**
* @}
*/
/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
* @{
*/
/* Filter state functions *****************************************************/
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
* @{
*/
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \
((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
((MODE) == DFSDM_CHANNEL_DUAL_MODE))
#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3))
#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC5_ORDER))
#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xF)
#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
((CHANNEL) == DFSDM_CHANNEL_1) || \
((CHANNEL) == DFSDM_CHANNEL_2) || \
((CHANNEL) == DFSDM_CHANNEL_3) || \
((CHANNEL) == DFSDM_CHANNEL_4) || \
((CHANNEL) == DFSDM_CHANNEL_5) || \
((CHANNEL) == DFSDM_CHANNEL_6) || \
((CHANNEL) == DFSDM_CHANNEL_7))
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FF))
#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
((MODE) == DFSDM_CONTINUOUS_CONV_ON))
/**
* @}
*/
/* End of private macros ------------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_DFSDM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h
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@@ -0,0 +1,629 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DMA2D_H
#define __STM32H7xx_HAL_DMA2D_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Types DMA2D Exported Types
* @{
*/
#define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */
/**
* @brief DMA2D color Structure definition
*/
typedef struct
{
uint32_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
} DMA2D_ColorTypeDef;
/**
* @brief DMA2D CLUT Structure definition
*/
typedef struct
{
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
This parameter can be one value of @ref DMA2D_CLUT_CM. */
uint32_t Size; /*!< Configures the DMA2D CLUT size.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
} DMA2D_CLUTCfgTypeDef;
/**
* @brief DMA2D Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_Mode. */
uint32_t ColorMode; /*!< Configures the color format of the output image.
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted */
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
for the output pixel format converter.
This parameter can be one value of @ref DMA2D_RB_Swap. */
} DMA2D_InitTypeDef;
/**
* @brief DMA2D Layer structure definition
*/
typedef struct
{
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
@note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
- InputAlpha[8:15] is the green value GREEN[0:7]
- InputAlpha[0:7] is the blue value BLUE[0:7]. */
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
This parameter can be one value of @ref DMA2D_Alpha_Inverted.*/
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
This parameter can be one value of @ref DMA2D_RB_Swap. */
uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */
} DMA2D_LayerCfgTypeDef;
/**
* @brief HAL DMA2D State structures definition
*/
typedef enum
{
HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
}HAL_DMA2D_StateTypeDef;
/**
* @brief DMA2D handle Structure definition
*/
typedef struct __DMA2D_HandleTypeDef
{
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
* @{
*/
/** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{
*/
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
/**
* @}
*/
/** @defgroup DMA2D_Mode DMA2D Mode
* @{
*/
#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
/**
* @}
*/
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
* @{
*/
#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
/**
* @}
*/
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{
*/
#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
#define DMA2D_INPUT_YCBCR ((uint32_t)0x0000000BU) /*!< YCbCr color mode */
/**
* @}
*/
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
with original alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
* @{
*/
#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
* @{
*/
#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */
#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */
/**
* @}
*/
/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
* @{
*/
#define DMA2D_NO_CSS ((uint32_t)0x00000000) /*!< No chroma sub-sampling 4:4:4 */
#define DMA2D_CSS_422 ((uint32_t)0x00000001) /*!< chroma sub-sampling 4:2:2 */
#define DMA2D_CSS_420 ((uint32_t)0x00000002) /*!< chroma sub-sampling 4:2:0 */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{
*/
#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
/**
* @}
*/
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
* @{
*/
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
/**
* @}
*/
/** @defgroup DMA2D_Flags DMA2D Flags
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
/**
* @}
*/
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
* @{
*/
/** @brief Reset DMA2D handle state
* @param __HANDLE__: specifies the DMA2D handle.
* @retval None
*/
#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
/**
* @brief Enable the DMA2D.
* @param __HANDLE__: DMA2D handle
* @retval None.
*/
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
/* Interrupt & Flag management */
/**
* @brief Get the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle
* @param __FLAG__: flag to check.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
* @retval The state of FLAG.
*/
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clear the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
* @retval None
*/
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
/**
* @brief Enable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA2D interrupt source is enabled or not.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval The state of INTERRUPT source.
*/
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
* @{
*/
/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
* @{
*/
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
* @{
*/
#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
/**
* @}
*/
/** @defgroup DMA2D_Color_Value DMA2D Color Value
* @{
*/
#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
/**
* @}
*/
/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */
/**
* @}
*/
/** @defgroup DMA2D_Size DMA2D Size
* @{
*/
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D maximum CLUT size */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4) || ((INPUT_CM) == DMA2D_INPUT_YCBCR))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
((AlphaMode) == DMA2D_COMBINE_ALPHA))
#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
((RB_Swap) == DMA2D_RB_SWAP))
#define IS_DMA2D_CHROMA_SUB_SAMPLING (CSS) (((CSS) == DMA2D_NO_CSS) || \
((CSS) == DMA2D_CSS_422) || \
((CSS) == DMA2D_CSS_420))
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_DMA2D_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h
+324
View File
@@ -0,0 +1,324 @@
/**
******************************************************************************
* @file stm32h7xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_DMA_EX_H
#define __STM32H7xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @brief DMAEx Exported types
* @{
*/
/**
* @brief HAL DMA Memory definition
*/
typedef enum
{
MEMORY0 = 0x00U, /*!< Memory 0 */
MEMORY1 = 0x01U, /*!< Memory 1 */
}HAL_DMA_MemoryTypeDef;
/**
* @brief HAL DMAMUX Synchronization configuration structure definition
*/
typedef struct
{
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
This parameter can take the value ENABLE or DISABLE*/
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
This parameter can take the value ENABLE or DISABLE */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.
This parameters can be in the range 1 to 32 */
}HAL_DMA_MuxSyncConfigTypeDef;
/**
* @brief HAL DMAMUX request generator parameters structure definition
*/
typedef struct
{
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event.
This parameters can be in the range 1 to 32 */
}HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMA Exported Constants
* @brief DMAEx Exported constants
* @{
*/
/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection
* @brief DMAEx MUX SyncSignalID selection
* @{
*/
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 1U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 2U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 3U /*!< D2 Domain synchronization Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_SYNC_LPTIM2_OUT 4U /*!< D2 Domain synchronization Signal is LPTIM2 OUT */
#define HAL_DMAMUX1_SYNC_LPTIM3_OUT 5U /*!< D2 Domain synchronization Signal is LPTIM3 OUT */
#define HAL_DMAMUX1_SYNC_EXTI0 6U /*!< D2 Domain synchronization Signal is EXTI0 IT */
#define HAL_DMAMUX1_SYNC_TIM12_TRGO 7U /*!< D2 Domain synchronization Signal is TIM12 TRGO */
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel0 Event */
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 1U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel1 Event */
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 2U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel2 Event */
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 3U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel3 Event */
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 4U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel4 Event */
#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 5U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel5 Event */
#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP 6U /*!< D3 Domain synchronization Signal is LPUART1 RX Wakeup */
#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP 7U /*!< D3 Domain synchronization Signal is LPUART1 TX Wakeup */
#define HAL_DMAMUX2_SYNC_LPTIM2_OUT 8U /*!< D3 Domain synchronization Signal is LPTIM2 output */
#define HAL_DMAMUX2_SYNC_LPTIM3_OUT 9U /*!< D3 Domain synchronization Signal is LPTIM3 output */
#define HAL_DMAMUX2_SYNC_I2C4_WKUP 10U /*!< D3 Domain synchronization Signal is I2C4 Wakeup */
#define HAL_DMAMUX2_SYNC_SPI6_WKUP 11U /*!< D3 Domain synchronization Signal is SPI6 Wakeup */
#define HAL_DMAMUX2_SYNC_COMP1_OUT 12U /*!< D3 Domain synchronization Signal is Comparator 1 output */
#define HAL_DMAMUX2_SYNC_RTC_WKUP 13U /*!< D3 Domain synchronization Signal is RTC Wakeup */
#define HAL_DMAMUX2_SYNC_EXTI0 14U /*!< D3 Domain synchronization Signal is EXTI0 IT */
#define HAL_DMAMUX2_SYNC_EXTI2 15U /*!< D3 Domain synchronization Signal is EXTI2 IT */
/**
* @}
*/
/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection
* @brief DMAEx MUX SyncPolarity selection
* @{
*/
#define HAL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< block synchronization events */
#define HAL_DMAMUX_SYNC_RISING DMAMUX_CxCR_SPOL_0 /*!< synchronize with rising edge events */
#define HAL_DMAMUX_SYNC_FALLING DMAMUX_CxCR_SPOL_1 /*!< synchronize with falling edge events */
#define HAL_DMAMUX_SYNC_RISING_FALLING DMAMUX_CxCR_SPOL /*!< synchronize with rising and falling edge events */
/**
* @}
*/
/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection
* @brief DMAEx MUX SignalGeneratorID selection
* @{
*/
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< D2 domain Request generator Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< D2 domain Request generator Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< D2 domain Request generator Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< D2 domain Request generator Signal is LPTIM1 OUT */
#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< D2 domain Request generator Signal is LPTIM2 OUT */
#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< D2 domain Request generator Signal is LPTIM3 OUT */
#define HAL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< D2 domain Request generator Signal is EXTI0 IT */
#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< D2 domain Request generator Signal is TIM12 TRGO */
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< D3 domain Request generator Signal is DMAMUX2 Channel0 Event */
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< D3 domain Request generator Signal is DMAMUX2 Channel1 Event */
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< D3 domain Request generator Signal is DMAMUX2 Channel2 Event */
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< D3 domain Request generator Signal is DMAMUX2 Channel3 Event */
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< D3 domain Request generator Signal is DMAMUX2 Channel4 Event */
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< D3 domain Request generator Signal is DMAMUX2 Channel5 Event */
#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< D3 domain Request generator Signal is DMAMUX2 Channel6 Event */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< D3 domain Request generator Signal is LPUART1 RX Wakeup */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< D3 domain Request generator Signal is LPUART1 TX Wakeup */
#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< D3 domain Request generator Signal is LPTIM2 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< D3 domain Request generator Signal is LPTIM2 OUT */
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< D3 domain Request generator Signal is LPTIM3 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< D3 domain Request generator Signal is LPTIM3 OUT */
#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< D3 domain Request generator Signal is LPTIM4 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< D3 domain Request generator Signal is LPTIM5 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< D3 domain Request generator Signal is I2C4 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< D3 domain Request generator Signal is SPI6 Wakeup */
#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< D3 domain Request generator Signal is Comparator 1 output */
#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< D3 domain Request generator Signal is Comparator 2 output */
#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< D3 domain Request generator Signal is RTC Wakeup */
#define HAL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< D3 domain Request generator Signal is EXTI0 */
#define HAL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< D3 domain Request generator Signal is EXTI2 */
#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< D3 domain Request generator Signal is I2C4 IT Event */
#define HAL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< D3 domain Request generator Signal is SPI6 IT */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< D3 domain Request generator Signal is LPUART1 Tx IT */
#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< D3 domain Request generator Signal is LPUART1 Rx IT */
#define HAL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< D3 domain Request generator Signal is ADC3 IT */
#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< D3 domain Request generator Signal is ADC3 Analog Watchdog 1 output */
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< D3 domain Request generator Signal is BDMA Channel 0 IT */
#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< D3 domain Request generator Signal is BDMA Channel 1 IT */
/**
* @}
*/
/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection
* @brief DMAEx MUX RequestGeneneratorPolarity selection
* @{
*/
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
* @brief DMAEx Exported functions
* @{
*/
/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMA Private Macros
* @brief DMAEx private macros
* @{
*/
#define IS_D2_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)
#define IS_D3_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
((EVENT) == ENABLE))
#define IS_D2_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)
#define IS_D3_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0) && ((REQUEST_NUMBER) <= 32))
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
* @brief DMAEx Private functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_DMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_eth_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of ETH HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H7xx_HAL_ETH_EX_H
#define STM32H7xx_HAL_ETH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup ETHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ETHEx_Exported_Types ETHEx Exported Types
* @{
*/
/**
* @brief ETH RX VLAN structure definition
*/
typedef struct{
FunctionalState InnerVLANTagInStatus; /*!< Enables or disables Inner VLAN Tag in Rx Status */
uint32_t StripInnerVLANTag; /*!< Sets the Inner VLAN Tag Stripping on Receive
This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */
FunctionalState InnerVLANTag; /*!< Enables or disables Inner VLAN Tag */
FunctionalState DoubleVLANProcessing; /*!< Enable or Disable double VLAN processing */
FunctionalState VLANTagHashTableMatch; /*!< Enable or Disable VLAN Tag Hash Table Match */
FunctionalState VLANTagInStatus; /*!< Enable or Disable VLAN Tag in Rx status */
uint32_t StripVLANTag; /*!< Set the VLAN Tag Stripping on Receive
This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */
uint32_t VLANTypeCheck; /*!< Enable or Disable VLAN Type Check
This parameter can be a value of @ref ETHEx_VLAN_Type_Check */
FunctionalState VLANTagInverceMatch; /*!< Enable or disable VLAN Tag Inverse Match */
}ETH_RxVLANConfigTypeDef;
/**
*
*/
/**
* @brief ETH TX VLAN structure definition
*/
typedef struct{
FunctionalState SourceTxDesc; /*!< Enable or Disable VLAN tag source from DMA tx descriptors */
FunctionalState SVLANType; /*!< Enable or Disable insertion of SVLAN type */
uint32_t VLANTagControl; /*!< Sets the VLAN tag control in tx packets
This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */
}ETH_TxVLANConfigTypeDef;
/**
*
*/
/**
* @brief ETH L3 filter structure definition
*/
typedef struct{
uint32_t Protocol; /*!< Sets the L3 filter protocol to IPv4 or IPv6
This parameter can be a value of @ref ETHEx_L3_Protocol */
uint32_t SrcAddrFilterMatch; /*!< Sets the L3 filter source address match
This parameter can be a value of @ref ETHEx_L3_Source_Match */
uint32_t DestAddrFilterMatch; /*!< Sets the L3 filter destination address match
This parameter can be a value of @ref ETHEx_L3_Destination_Match */
uint32_t SrcAddrHigherBitsMatch; /*!< Sets the L3 filter source address higher bits match
This parameter can be a value from 0 to 31 */
uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match
This parameter can be a value from 0 to 31 */
uint32_t Ip4SrcAddr; /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used
This parameter can be a value from 0x0 to 0xFFFFFFFF */
uint32_t Ip4DestAddr; /*!< Sets the L3 filter IPv4 destination address if IPv4 protocol is used
This parameter can be a value from 0 to 0xFFFFFFFF */
uint32_t Ip6Addr[4]; /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used
This parameter must be a table of 4 words (4* 32 bits) */
}ETH_L3FilterConfigTypeDef;
/**
*
*/
/**
* @brief ETH L4 filter structure definition
*/
typedef struct{
uint32_t Protocol; /*!< Sets the L4 filter protocol to TCP or UDP
This parameter can be a value of @ref ETHEx_L4_Protocol */
uint32_t SrcPortFilterMatch; /*!< Sets the L4 filter source port match
This parameter can be a value of @ref ETHEx_L4_Source_Match */
uint32_t DestPortFilterMatch; /*!< Sets the L4 filter destination port match
This parameter can be a value of @ref ETHEx_L4_Destination_Match */
uint32_t SourcePort; /*!< Sets the L4 filter source port
This parameter must be a value from 0x0 to 0xFFFF */
uint32_t DestinationPort; /*!< Sets the L4 filter destination port
This parameter must be a value from 0x0 to 0xFFFF */
}ETH_L4FilterConfigTypeDef;
/**
*
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants
* @{
*/
/** @defgroup ETHEx_LPI_Event ETHEx LPI Event
* @{
*/
#define ETH_TX_LPI_ENTRY ETH_MACLCSR_TLPIEN
#define ETH_TX_LPI_EXIT ETH_MACLCSR_TLPIEX
#define ETH_RX_LPI_ENTRY ETH_MACLCSR_RLPIEN
#define ETH_RX_LPI_EXIT ETH_MACLCSR_RLPIEX
/**
* @}
*/
/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter
* @{
*/
#define ETH_L3_FILTER_0 ((uint32_t)0x00000000)
#define ETH_L3_FILTER_1 ((uint32_t)0x0000000C)
/**
* @}
*/
/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter
* @{
*/
#define ETH_L4_FILTER_0 ((uint32_t)0x00000000)
#define ETH_L4_FILTER_1 ((uint32_t)0x0000000C)
/**
* @}
*/
/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol
* @{
*/
#define ETH_L3_IPV6_MATCH ETH_MACL3L4CR_L3PEN
#define ETH_L3_IPV4_MATCH ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match
* @{
*/
#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3SAM
#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)
#define ETH_L3_SRC_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match
* @{
*/
#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L3DAM
#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)
#define ETH_L3_DEST_ADDR_MATCH_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol
* @{
*/
#define ETH_L4_UDP_MATCH ETH_MACL3L4CR_L4PEN
#define ETH_L4_TCP_MATCH ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match
* @{
*/
#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4SPM
#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM)
#define ETH_L4_SRC_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match
* @{
*/
#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE ETH_MACL3L4CR_L4DPM
#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)
#define ETH_L4_DEST_PORT_MATCH_DISABLE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping
* @{
*/
#define ETH_INNERVLANTAGRXSTRIPPING_NONE ETH_MACVTR_EIVLS_DONOTSTRIP
#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EIVLS_STRIPIFPASS
#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS
#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EIVLS_ALWAYSSTRIP
/**
* @}
*/
/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping
* @{
*/
#define ETH_VLANTAGRXSTRIPPING_NONE ETH_MACVTR_EVLS_DONOTSTRIP
#define ETH_VLANTAGRXSTRIPPING_IFPASS ETH_MACVTR_EVLS_STRIPIFPASS
#define ETH_VLANTAGRXSTRIPPING_IFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS
#define ETH_VLANTAGRXSTRIPPING_ALWAYS ETH_MACVTR_EVLS_ALWAYSSTRIP
/**
* @}
*/
/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check
* @{
*/
#define ETH_VLANTYPECHECK_DISABLE ETH_MACVTR_DOVLTC
#define ETH_VLANTYPECHECK_SVLAN (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)
#define ETH_VLANTYPECHECK_CVLAN ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control
* @{
*/
#define ETH_VLANTAGCONTROL_NONE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)
#define ETH_VLANTAGCONTROL_DELETE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)
#define ETH_VLANTAGCONTROL_INSERT (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)
#define ETH_VLANTAGCONTROL_REPLACE (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)
/**
* @}
*/
/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag
* @{
*/
#define ETH_INNER_TX_VLANTAG ((uint32_t)0x00000001U)
#define ETH_OUTER_TX_VLANTAG ((uint32_t)0x00000000U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ETHEx_Exported_Functions
* @{
*/
/** @addtogroup ETHEx_Exported_Functions_Group1
* @{
*/
/* MAC ARP Offloading APIs ***************************************************/
void HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);
void HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);
void HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress);
/* MAC L3 L4 Filtering APIs ***************************************************/
void HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);
void HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);
HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);
/* MAC VLAN Processing APIs ************************************************/
void HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);
void HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);
void HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);
HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);
void HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);
/* Energy Efficient Ethernet APIs *********************************************/
void HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);
void HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);
uint32_t HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H7xx_HAL_ETH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h
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/**
******************************************************************************
* @file stm32h7xx_hal_flash.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_FLASH_H
#define __STM32H7xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Procedure structure definition
*/
typedef enum
{
FLASH_PROC_NONE = 0U,
FLASH_PROC_SECTERASE_BANK1,
FLASH_PROC_MASSERASE_BANK1,
FLASH_PROC_PROGRAM_BANK1,
FLASH_PROC_SECTERASE_BANK2,
FLASH_PROC_MASSERASE_BANK2,
FLASH_PROC_PROGRAM_BANK2,
FLASH_PROC_ALLBANK_MASSERASE
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in IT context */
__IO uint8_t VoltageForErase; /*!< Internal variable to provide voltage range selected by user in IT context */
__IO uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */
__IO uint32_t Address; /*!< Internal variable to save address selected for program */
HAL_LockTypeDef Lock; /*!< FLASH locking object */
__IO uint32_t ErrorCode; /*!< FLASH error code */
}FLASH_ProcessTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_Error_Code FLASH Error Code
* @brief FLASH Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000001U) /*!< Write Protection Error */
#define HAL_FLASH_ERROR_PGS ((uint32_t)0x00000002U) /*!< Program Sequence Error */
#define HAL_FLASH_ERROR_STRB ((uint32_t)0x00000004U) /*!< Strobe Error */
#define HAL_FLASH_ERROR_INC ((uint32_t)0x00000008U) /*!< Inconsistency Error */
#define HAL_FLASH_ERROR_OPE ((uint32_t)0x00000010U) /*!< Operation Error */
#define HAL_FLASH_ERROR_RDP ((uint32_t)0x00000020U) /*!< Read Protection Error */
#define HAL_FLASH_ERROR_RDS ((uint32_t)0x00000040U) /*!< Read Secured Error */
#define HAL_FLASH_ERROR_SNECC ((uint32_t)0x00000080U) /*!< Single Detection ECC */
#define HAL_FLASH_ERROR_DBECC ((uint32_t)0x00000100U) /*!< Double Detection ECC */
#define HAL_FLASH_ERROR_WRP_BANK1 ((uint32_t)0x00000001U) /*!< Write Protection Error on Bank 1 */
#define HAL_FLASH_ERROR_PGS_BANK1 ((uint32_t)0x00000002U) /*!< Program Sequence Error on Bank 1 */
#define HAL_FLASH_ERROR_STRB_BANK1 ((uint32_t)0x00000004U) /*!< Strobe Error on Bank 1 */
#define HAL_FLASH_ERROR_INC_BANK1 ((uint32_t)0x00000008U) /*!< Inconsistency Error on Bank 1 */
#define HAL_FLASH_ERROR_OPE_BANK1 ((uint32_t)0x00000010U) /*!< Operation Error on Bank 1 */
#define HAL_FLASH_ERROR_RDP_BANK1 ((uint32_t)0x00000020U) /*!< Read Protection Error on Bank 1 */
#define HAL_FLASH_ERROR_RDS_BANK1 ((uint32_t)0x00000040U) /*!< Read Secured Error on Bank 1 */
#define HAL_FLASH_ERROR_SNECC_BANK1 ((uint32_t)0x00000080U) /*!< Single Detection ECC on Bank 1 */
#define HAL_FLASH_ERROR_DBECC_BANK1 ((uint32_t)0x00000100U) /*!< Double Detection ECC on Bank 1 */
#define HAL_FLASH_ERROR_WRP_BANK2 ((uint32_t)0x00001000U) /*!< Write Protection Error on Bank 2 */
#define HAL_FLASH_ERROR_PGS_BANK2 ((uint32_t)0x00002000U) /*!< Program Sequence Error on Bank 2 */
#define HAL_FLASH_ERROR_STRB_BANK2 ((uint32_t)0x00004000U) /*!< Strobe Error on Bank 2 */
#define HAL_FLASH_ERROR_INC_BANK2 ((uint32_t)0x00008000U) /*!< Inconsistency Error on Bank 2 */
#define HAL_FLASH_ERROR_OPE_BANK2 ((uint32_t)0x00010000U) /*!< Operation Error on Bank 2 */
#define HAL_FLASH_ERROR_RDP_BANK2 ((uint32_t)0x00020000U) /*!< Read Protection Error on Bank 2 */
#define HAL_FLASH_ERROR_RDS_BANK2 ((uint32_t)0x00040000U) /*!< Read Secured Error on Bank 2 */
#define HAL_FLASH_ERROR_SNECC_BANK2 ((uint32_t)0x00080000U) /*!< Single Detection ECC on Bank 2 */
#define HAL_FLASH_ERROR_DBECC_BANK2 ((uint32_t)0x00100000U) /*!< Double Detection ECC on Bank 2 */
#define HAL_FLASH_ERROR_OB_CHANGE ((uint32_t)0x01000000U) /*!< Option Byte Change Error */
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_FLASHWORD ((uint32_t)0x03U) /*!< Program a flash word (256-bit) at a specified address */
/**
* @}
*/
/** @defgroup FLASH_Flag_definition FLASH Flag definition
* @brief Flag definition
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_WDW FLASH_SR_WDW /*!< Waiting for Data to Write on flag */
#define FLASH_FLAG_QW FLASH_SR_QW /*!< Write Waiting in Operation Queue on flag */
#define FLASH_FLAG_CRC_BUSY FLASH_SR_CRC_BUSY /*!< CRC module is working on flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< End Of Program on flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< Write Protection Error on flag */
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< Program Sequence Error on flag */
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< strobe Error on flag */
#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< Inconsistency Error on flag */
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< Operation Error on flag */
#define FLASH_FLAG_RDPERR FLASH_SR_RDPERR /*!< Read Protection Error on flag */
#define FLASH_FLAG_RDSERR FLASH_SR_RDSERR /*!< Read Secured Error on flag */
#define FLASH_FLAG_SNECCERR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on flag */
#define FLASH_FLAG_DBECCERR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on flag */
#define FLASH_FLAG_CRCEND FLASH_SR_CRCEND /*!< CRC module completes on bank flag */
#define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY /*!< FLASH Bank 1 Busy flag */
#define FLASH_FLAG_WBNE_BANK1 FLASH_SR_WBNE /*!< Waiting for Data to Write on Bank 1 flag */
#define FLASH_FLAG_QW_BANK1 FLASH_SR_QW /*!< Write Waiting in Operation Queue on Bank 1 flag */
#define FLASH_FLAG_CRC_BUSY_BANK1 FLASH_SR_CRC_BUSY /*!< CRC module is working on Bank 1 flag */
#define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP /*!< End Of Program on Bank 1 flag */
#define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPERR /*!< Write Protection Error on Bank 1 flag */
#define FLASH_FLAG_PGSERR_BANK1 FLASH_SR_PGSERR /*!< Program Sequence Error on Bank 1 flag */
#define FLASH_FLAG_STRBER_BANK1R FLASH_SR_STRBERR /*!< strobe Error on Bank 1 flag */
#define FLASH_FLAG_INCERR_BANK1 FLASH_SR_INCERR /*!< Inconsistency Error on Bank 1 flag */
#define FLASH_FLAG_OPERR_BANK1 FLASH_SR_OPERR /*!< Operation Error on Bank 1 flag */
#define FLASH_FLAG_RDPERR_BANK1 FLASH_SR_RDPERR /*!< Read Protection Error on Bank 1 flag */
#define FLASH_FLAG_RDSERR_BANK1 FLASH_SR_RDSERR /*!< Read Secured Error on Bank 1 flag */
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_SR_SNECCERR /*!< Single ECC Error Correction on Bank 1 flag */
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_SR_DBECCERR /*!< Double Detection ECC Error on Bank 1 flag */
#define FLASH_FLAG_CRCEND_BANK1 FLASH_SR_CRCEND /*!< CRC module completes on bank Bank 1 flag */
#define FLASH_FLAG_ALL_ERRORS_BANK1 (FLASH_FLAG_WRPERR_BANK1 | FLASH_FLAG_PGSERR_BANK1 | \
FLASH_FLAG_STRBER_BANK1R | FLASH_FLAG_INCERR_BANK1 | \
FLASH_FLAG_OPERR_BANK1 | FLASH_FLAG_RDPERR_BANK1 | \
FLASH_FLAG_RDSERR_BANK1 | FLASH_FLAG_SNECCE_BANK1RR | \
FLASH_FLAG_DBECCE_BANK1RR)
#define FLASH_FLAG_ALL_BANK1 (FLASH_FLAG_BSY_BANK1 | FLASH_FLAG_WBNE_BANK1 | \
FLASH_FLAG_QW_BANK1 | FLASH_FLAG_CRC_BUSY_BANK1 | \
FLASH_FLAG_EOP_BANK1 | FLASH_FLAG_CRCEND_BANK1 | \
FLASH_FLAG_ALL_ERRORS_BANK1)
#define FLASH_FLAG_BSY_BANK2 (FLASH_SR_BSY | 0x80000000U) /*!< FLASH Bank 2 Busy flag */
#define FLASH_FLAG_WBNE_BANK2 (FLASH_SR_WBNE | 0x80000000U) /*!< Waiting for Data to Write on Bank 2 flag */
#define FLASH_FLAG_QW_BANK2 (FLASH_SR_QW | 0x80000000U) /*!< Write Waiting in Operation Queue on Bank 2 flag */
#define FLASH_FLAG_CRC_BUSY_BANK2 (FLASH_SR_CRC_BUSY | 0x80000000U) /*!< CRC module is working on Bank 2 flag */
#define FLASH_FLAG_EOP_BANK2 (FLASH_SR_EOP | 0x80000000U) /*!< End Of Program on Bank 2 flag */
#define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR_WRPERR | 0x80000000U) /*!< Write Protection Error on Bank 2 flag */
#define FLASH_FLAG_PGSERR_BANK2 (FLASH_SR_PGSERR | 0x80000000U) /*!< Program Sequence Error on Bank 2 flag */
#define FLASH_FLAG_STRBER_BANK2R (FLASH_SR_STRBERR | 0x80000000U) /*!< Strobe Error on Bank 2 flag */
#define FLASH_FLAG_INCERR_BANK2 (FLASH_SR_INCERR | 0x80000000U) /*!< Inconsistency Error on Bank 2 flag */
#define FLASH_FLAG_OPERR_BANK2 (FLASH_SR_OPERR | 0x80000000U) /*!< Operation Error on Bank 2 flag */
#define FLASH_FLAG_RDPERR_BANK2 (FLASH_SR_RDPERR | 0x80000000U) /*!< Read Protection Error on Bank 2 flag */
#define FLASH_FLAG_RDSERR_BANK2 (FLASH_SR_RDSERR | 0x80000000U) /*!< Read Secured Error on Bank 2 flag */
#define FLASH_FLAG_SNECCE_BANK2RR (FLASH_SR_SNECCERR | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 flag */
#define FLASH_FLAG_DBECCE_BANK2RR (FLASH_SR_DBECCERR | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 flag */
#define FLASH_FLAG_CRCEND_BANK2 (FLASH_SR_CRCEND | 0x80000000U) /*!< CRC module completes on bank Bank 2 flag */
#define FLASH_FLAG_ALL_ERRORS_BANK2 (FLASH_FLAG_WRPERR_BANK2 | FLASH_FLAG_PGSERR_BANK2 | \
FLASH_FLAG_STRBER_BANK2R | FLASH_FLAG_INCERR_BANK2 | \
FLASH_FLAG_OPERR_BANK2 | FLASH_FLAG_RDPERR_BANK2 | \
FLASH_FLAG_RDSERR_BANK2 | FLASH_FLAG_SNECCE_BANK2RR | \
FLASH_FLAG_DBECCE_BANK2RR)
#define FLASH_FLAG_ALL_BANK2 (FLASH_FLAG_BSY_BANK2 | FLASH_FLAG_WBNE_BANK2 | \
FLASH_FLAG_QW_BANK2 | FLASH_FLAG_CRC_BUSY_BANK2 | \
FLASH_FLAG_EOP_BANK2 | FLASH_FLAG_CRCEND_BANK2 | \
FLASH_FLAG_ALL_ERRORS_BANK2)
/**
* @}
*/
/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
* @brief FLASH Interrupt definition
* @{
*/
#define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE /*!< End of FLASH Bank 1 Operation Interrupt source */
#define FLASH_IT_WRPERR_BANK1 FLASH_CR_WRPERRIE /*!< Write Protection Error on Bank 1 Interrupt source */
#define FLASH_IT_PGSERR_BANK1 FLASH_CR_PGSERRIE /*!< Program Sequence Error on Bank 1 Interrupt source */
#define FLASH_IT_STRBERR_BANK1 FLASH_CR_STRBERRIE /*!< Strobe Error on Bank 1 Interrupt source */
#define FLASH_IT_INCERR_BANK1 FLASH_CR_INCERRIE /*!< Inconsistency Error on Bank 1 Interrupt source */
#define FLASH_IT_OPERR_BANK1 FLASH_CR_OPERRIE /*!< Operation Error on Bank 1 Interrupt source */
#define FLASH_IT_RDPERR_BANK1 FLASH_CR_RDPERRIE /*!< Read protection Error on Bank 1 Interrupt source */
#define FLASH_IT_RDSERR_BANK1 FLASH_CR_RDSERRIE /*!< Read Secured Error on Bank 1 Interrupt source */
#define FLASH_IT_SNECCERR_BANK1 FLASH_CR_SNECCERRIE /*!< Single ECC Error Correction on Bank 1 Interrupt source */
#define FLASH_IT_DBECCERR_BANK1 FLASH_CR_DBECCERRIE /*!< Double Detection ECC Error on Bank 1 Interrupt source */
#define FLASH_IT_CRCEND_BANK1 FLASH_CR_CRCENDIE /*!< CRC End on Bank 1 Interrupt source */
#define FLASH_IT_ALL_BANK1 (FLASH_IT_EOP_BANK1 | FLASH_IT_WRPERR_BANK1 | \
FLASH_IT_PGSERR_BANK1 | FLASH_IT_STRBERR_BANK1 | \
FLASH_IT_INCERR_BANK1 | FLASH_IT_OPERR_BANK1 | \
FLASH_IT_RDPERR_BANK1 | FLASH_IT_RDSERR_BANK1 | \
FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
FLASH_CR_CRCENDIE )
#define FLASH_IT_EOP_BANK2 (FLASH_CR_EOPIE | 0x80000000U) /*!< End of FLASH Bank 2 Operation Interrupt source */
#define FLASH_IT_WRPERR_BANK2 (FLASH_CR_WRPERRIE | 0x80000000U) /*!< Write Protection Error on Bank 2 Interrupt source */
#define FLASH_IT_PGSERR_BANK2 (FLASH_CR_PGSERRIE | 0x80000000U) /*!< Program Sequence Error on Bank 2 Interrupt source */
#define FLASH_IT_STRBERR_BANK2 (FLASH_CR_STRBERRIE | 0x80000000U) /*!< Strobe Error on Bank 2 Interrupt source */
#define FLASH_IT_INCERR_BANK2 (FLASH_CR_INCERRIE | 0x80000000U) /*!< Inconsistency Error on Bank 2 Interrupt source */
#define FLASH_IT_OPERR_BANK2 (FLASH_CR_OPERRIE | 0x80000000U) /*!< Operation Error on Bank 2 Interrupt source */
#define FLASH_IT_RDPERR_BANK2 (FLASH_CR_RDPERRIE | 0x80000000U) /*!< Read protection Error on Bank 2 Interrupt source */
#define FLASH_IT_RDSERR_BANK2 (FLASH_CR_RDSERRIE | 0x80000000U) /*!< Read Secured Error on Bank 2 Interrupt source */
#define FLASH_IT_SNECCERR_BANK2 (FLASH_CR_SNECCERRIE | 0x80000000U) /*!< Single ECC Error Correction on Bank 2 Interrupt source */
#define FLASH_IT_DBECCERR_BANK2 (FLASH_CR_DBECCERRIE | 0x80000000U) /*!< Double Detection ECC Error on Bank 2 Interrupt source */
#define FLASH_IT_CRCEND_BANK2 (FLASH_CR_CRCENDIE | 0x80000000U) /*!< CRC End on Bank 2 Interrupt source */
#define FLASH_IT_ALL_BANK2 (FLASH_IT_EOP_BANK2 | FLASH_IT_WRPERR_BANK1 | \
FLASH_IT_PGSERR_BANK2 | FLASH_IT_STRBERR_BANK1 | \
FLASH_IT_INCERR_BANK2 | FLASH_IT_OPERR_BANK1 | \
FLASH_IT_RDPERR_BANK2 | FLASH_IT_RDSERR_BANK1 | \
FLASH_CR_SNECCERRIE | FLASH_CR_DBECCERRIE | \
FLASH_CR_CRCENDIE )
/**
* @}
*/
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
*/
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFFCFU)
/**
* @}
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_KEY1 ((uint32_t)0x45670123U)
#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
/**
* @}
*/
/** @defgroup FLASH_Sectors FLASH Sectors
* @{
*/
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */
#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__: FLASH Latency
* The value of this parameter depend on device used within the same series
* @retval none
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* The value of this parameter depend on device used within the same series
*/
#define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
* In case of Bank 1 This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
* @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
* @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
* @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
* @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
* @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
* @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
* @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
* In case of Bank 2 This parameter can be any combination of the following values: *
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
* @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
* @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
* @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
* @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
* @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 |= (__INTERRUPT__))
#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFF))
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
__HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \
__HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
* In case of Bank 1 This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP_BANK1 : End of FLASH Bank 1 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK1 : Write Protection Error on Bank 1 Interrupt source
* @arg FLASH_IT_PGSERR_BANK1 : Program Sequence Error on Bank 1 Interrupt source
* @arg FLASH_IT_STRBERR_BANK1 : Strobe Error on Bank 1 Interrupt source
* @arg FLASH_IT_INCERR_BANK1 : Inconsistency Error on Bank 1 Interrupt source
* @arg FLASH_IT_OPERR_BANK1 : Operation Error on Bank 1 Interrupt source
* @arg FLASH_IT_RDPERR_BANK1 : Read protection Error on Bank 1 Interrupt source
* @arg FLASH_IT_RDSERR_BANK1 : Read secure Error on Bank 1 Interrupt source
* @arg FLASH_IT_SNECCERR_BANK1 : Single ECC Error Correction on Bank 1 Interrupt source
* @arg FLASH_IT_DBECCERR_BANK1 : Double Detection ECC Error on Bank 1 Interrupt source
* @arg FLASH_IT_CRCEND_BANK1 : CRC End on Bank 1 Interrupt source
* In case of Bank 2 This parameter can be any combination of the following values: *
* @arg FLASH_IT_EOP_BANK2 : End of FLASH Bank 2 Operation Interrupt source
* @arg FLASH_IT_WRPERR_BANK2 : Write Protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_PGSERR_BANK2 : Program Sequence Error on Bank 2 Interrupt source
* @arg FLASH_IT_STRBERR_BANK2 : Strobe Error on Bank 2 Interrupt source
* @arg FLASH_IT_INCERR_BANK2 : Inconsistency Error on Bank 2 Interrupt source
* @arg FLASH_IT_OPERR_BANK2 : Operation Error on Bank 2 Interrupt source
* @arg FLASH_IT_RDPERR_BANK2 : Read protection Error on Bank 2 Interrupt source
* @arg FLASH_IT_RDSERR_BANK2 : Read secure Error on Bank 2 Interrupt source
* @arg FLASH_IT_SNECCERR_BANK2 : Single ECC Error Correction on Bank 2 Interrupt source
* @arg FLASH_IT_DBECCERR_BANK2 : Double Detection ECC Error on Bank 2 Interrupt source
* @arg FLASH_IT_CRCEND_BANK2 : CRC End on Bank 2 Interrupt source
* @retval none
*/
#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))
#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__) (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFF))
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \
__HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \
__HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))
/**
* @brief Checks whether the specified FLASH flag is set or not.
* @param __FLAG__: specifies the FLASH flag to check.
* In case of Bank 1 This parameter can be any combination of the following values :
* @arg FLASH_FLAG_BSY_BANK1 : FLASH Bank 1 Busy flag
* @arg FLASH_FLAG_WBNE_BANK1 : Waiting for Data to Write on Bank 1 flag
* @arg FLASH_FLAG_QW_BANK1 : Write Waiting in Operation Queue on Bank 1 flag
* @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
*
* In case of Bank 2 This parameter can be any combination of the following values :
* @arg FLASH_FLAG_BSY_BANK2 : FLASH Bank 2 Busy flag
* @arg FLASH_FLAG_WBNE_BANK2 : Waiting for Data to Write on Bank 2 flag
* @arg FLASH_FLAG_QW_BANK2 : Write Waiting in Operation Queue on Bank 2 flag
* @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))
#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__) (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFF)) == (((__FLAG__) & 0x7FFFFFFF)))
#define __HAL_FLASH_GET_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \
__HAL_FLASH_GET_FLAG_BANK2(__FLAG__))
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP_BANK1 : End Of Program on Bank 1 flag
* @arg FLASH_FLAG_WRPERR_BANK1 : Write Protection Error on Bank 1 flag
* @arg FLASH_FLAG_PGSERR_BANK1 : Program Sequence Error on Bank 1 flag
* @arg FLASH_FLAG_STRBER_BANK1 : Program Alignment Error on Bank 1 flag
* @arg FLASH_FLAG_INCERR_BANK1 : Inconsistency Error on Bank 1 flag
* @arg FLASH_FLAG_OPERR_BANK1 : Operation Error on Bank 1 flag
* @arg FLASH_FLAG_RDPERR_BANK1 : Read Protection Error on Bank 1 flag
* @arg FLASH_FLAG_RDSERR_BANK1 : Read secure Error on Bank 1 flag
* @arg FLASH_FLAG_SNECCE_BANK1 : Single ECC Error Correction on Bank 1 flag
* @arg FLASH_FLAG_DBECCE_BANK1 : Double Detection ECC Error on Bank 1 flag
* @arg FLASH_FLAG_CRCEND_BANK1 : CRC End on Bank 1 flag
*
* In case of Bank 2 This parameter can be any combination of the following values :
* @arg FLASH_FLAG_EOP_BANK2 : End Of Program on Bank 2 flag
* @arg FLASH_FLAG_WRPERR_BANK2 : Write Protection Error on Bank 2 flag
* @arg FLASH_FLAG_PGSERR_BANK2 : Program Sequence Error on Bank 2 flag
* @arg FLASH_FLAG_STRBER_BANK2 : Program Alignment Error on Bank 2 flag
* @arg FLASH_FLAG_INCERR_BANK2 : Inconsistency Error on Bank 2 flag
* @arg FLASH_FLAG_OPERR_BANK2 : Operation Error on Bank 2 flag
* @arg FLASH_FLAG_RDPERR_BANK2 : Read Protection Error on Bank 2 flag
* @arg FLASH_FLAG_RDSERR_BANK2 : Read secure Error on Bank 2 flag
* @arg FLASH_FLAG_SNECCE_BANK2 : Single ECC Error Correction on Bank 2 flag
* @arg FLASH_FLAG_DBECCE_BANK2 : Double Detection ECC Error on Bank 2 flag
* @arg FLASH_FLAG_CRCEND_BANK2 : CRC End on Bank 2 flag
* @retval none
*/
#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) WRITE_REG(FLASH->CCR1, (__FLAG__))
#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__) WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFF))
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (IS_FLASH_FLAG_BANK1(__FLAG__) ? __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \
__HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))
/**
* @}
*/
/* Include FLASH HAL Extension module */
#include "stm32h7xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
/* Program operation functions ***********************************************/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t DataAddress);
/* FLASH IRQ handler method */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
/* Option bytes control */
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
uint32_t HAL_FLASH_GetError(void);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);
HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions
* @{
*/
#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
/**
* @}
*/
/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions
* @{
*/
#define IS_FLASH_IT_BANK1(IT) (((IT) & FLASH_IT_ALL_BANK1) == (IT))
#define IS_FLASH_IT_BANK2(IT) (((IT) & FLASH_IT_ALL_BANK2) == (IT))
/**
* @}
*/
#define IS_FLASH_FLAG_BANK1(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
#define IS_FLASH_FLAG_BANK2(FLAG) (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
/** @defgroup FLASH_Address FLASH Address
* @{
*/
#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < (FLASH_BANK1_BASE + FLASH_BANK_SIZE) ))
#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) < (FLASH_BANK2_BASE + FLASH_BANK_SIZE) ))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
#define IS_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= (0x3FFF0000U))
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2))
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_FLASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h
+626
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@@ -0,0 +1,626 @@
/**
******************************************************************************
* @file stm32H7xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_FLASH_EX_H
#define __STM32H7xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< Mass erase or sector Erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
This parameter must be a value of @ref FLASHEx_Banks */
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
This parameter must be a value of @ref FLASH_Sectors */
uint32_t NbSectors; /*!< Number of sectors to be erased.
This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
This parameter must be a value of @ref FLASHEx_Voltage_Range */
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH Option Bytes Program structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a value of @ref FLASHEx_Option_Type */
uint32_t WRPState; /*!< Write protection activation or deactivation.
This parameter can be a value of @ref FLASHEx_WRP_State */
uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected.
The value of this parameter depend on device used within the same series */
uint32_t RDPLevel; /*!< Set the read protection level.
This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
uint32_t BORLevel; /*!< Set the BOR Level.
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */
uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config .
This parameter must be a value of @ref FLASHEx_Banks */
uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */
uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
This parameter must be a value between begin and end of a bank */
uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
This parameter must be a value between PCROP Start address and end of a bank */
uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
uint32_t BootAddr0; /*!< Boot Address 0.
This parameter must be a value between begin and end of a bank */
uint32_t BootAddr1; /*!< Boot Address 1.
This parameter must be a value between begin and end of a bank */
uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not
when RDP level decreased from Level 1 to Level 0 or during a mass erase.
This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
This parameter must be a value between begin and end of bank1 */
uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address .
This parameter must be a value between Start address and end of a bank1 */
} FLASH_OBProgramInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
/**
* @}
*/
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Flash program/erase by 8 bits */
#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)FLASH_CR_PSIZE_0) /*!< Flash program/erase by 16 bits */
#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)FLASH_CR_PSIZE_1) /*!< Flash program/erase by 32 bits */
#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)FLASH_CR_PSIZE) /*!< Flash program/erase by 64 bits */
/**
* @}
*/
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Type FLASH Option Type
* @{
*/
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
#define OPTIONBYTE_PCROP ((uint32_t)0x08U) /*!< PCROP option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x10U) /*!< BOR option byte configuration */
#define OPTIONBYTE_SECURE_AREA ((uint32_t)0x20U) /*!< secure area option byte configuration */
#define OPTIONBYTE_BOOTADD ((uint32_t)0x40U) /*!< BOOT ADD option byte configuration */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint32_t)0xAA00U)
#define OB_RDP_LEVEL_1 ((uint32_t)0x5500U)
#define OB_RDP_LEVEL_2 ((uint32_t)0xCC00U) /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
* @{
*/
#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */
#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
* @{
*/
#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
* @{
*/
#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
* @{
*/
#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_STOP) /*!< IWDG counter active in STOP mode */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
* @{
*/
#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE ((uint32_t)FLASH_OPTSR_FZ_IWDG_SDBY) /*!< IWDG counter active in STANDBY mode */
/**
* @}
*/
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
* @{
*/
#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
/**
* @}
*/
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
* @{
*/
#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */
/**
* @}
*/
/** @defgroup FLASHEx_Banks FLASH Banks
* @{
*/
#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */
#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */
#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
/**
* @}
*/
/** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP
* @{
*/
#define OB_PCROP_RDP_NOT_ERASE ((uint32_t)0x00000000U) /*!< PCROP area is not erased when the RDP level
is decreased from Level 1 to Level 0 or during a mass erase */
#define OB_PCROP_RDP_ERASE ((uint32_t)FLASH_PRAR_DMEP) /*!< PCROP area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
/**
* @}
*/
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_SECTOR_0 ((uint32_t)0x00000001U) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00000002U) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00000004U) /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 ((uint32_t)0x00000008U) /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 ((uint32_t)0x00000010U) /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 ((uint32_t)0x00000020U) /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 ((uint32_t)0x00000040U) /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 ((uint32_t)0x00000080U) /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All ((uint32_t)0x000000FFU) /*!< Write protection of all Sectors */
/**
* @}
*/
/** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY
* @{
*/
#define OB_SECURITY_DISABLE ((uint32_t)0x00000U) /*!< security enabled */
#define OB_SECURITY_ENABLE ((uint32_t)FLASH_OPTSR_SECURITY) /*!< security disabled */
/**
* @}
*/
/** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW
* @{
*/
#define OB_IWDG1_SW ((uint32_t)FLASH_OPTSR_IWDG1_SW) /*!< Hardware independent watchdog 1 */
#define OB_IWDG1_HW ((uint32_t)0x00000U) /*!< Software independent watchdog 1 */
/**
* @}
*/
/** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1
* @{
*/
#define OB_STOP_RST_D1 ((uint32_t)0x0000U) /*!< Reset generated when entering the D1 to stop mode */
#define OB_STOP_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STOP_D1) /*!< No reset generated when entering the D1 to stop mode */
/**
* @}
*/
/** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1
* @{
*/
#define OB_STDBY_RST_D1 ((uint32_t)0x0000U) /*!< Reset generated when entering the D1 to standby mode */
#define OB_STDBY_NO_RST_D1 ((uint32_t)FLASH_OPTSR_NRST_STBY_D1) /*!< No reset generated when entering the D1 to standby mode */
/**
* @}
*/
/** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK
* @{
*/
#define OB_SWAP_BANK_DISABLE ((uint32_t)0x00000U) /*!< Bank swap disabled */
#define OB_SWAP_BANK_ENABLE ((uint32_t)FLASH_OPTSR_SWAP_BANK_OPT) /*!< Bank swap enabled */
/**
* @}
*/
/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
* @{
*/
#define OB_IOHSLV_DISABLE ((uint32_t)0x00000000U) /*!< IOHSLV disabled */
#define OB_IOHSLV_ENABLE ((uint32_t)FLASH_OPTSR_IO_HSLV) /*!< IOHSLV enabled */
/**
* @}
*/
/** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION
* @{
*/
#define OB_BOOT_ADD0 ((uint32_t)0x01U) /*!< Select Boot Address 0 */
#define OB_BOOT_ADD1 ((uint32_t)0x02U) /*!< Select Boot Address 1 */
#define OB_BOOT_ADD_BOTH ((uint32_t)0x03U) /*!< Select Boot Address 0 and 1 */
/**
* @}
*/
/** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type
* @{
*/
#define OB_USER_NRST_STOP_D1 ((uint32_t)0x0001U) /*!< Reset when entering Stop mode selection*/
#define OB_USER_NRST_STDBY_D1 ((uint32_t)0x0002U) /*!< Reset when entering standby mode selection*/
#define OB_USER_IWDG_STOP ((uint32_t)0x0004U) /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY ((uint32_t)0x0008U) /*!< Independent watchdog counter freeze in standby mode */
#define OB_USER_ST_RAM_SIZE ((uint32_t)0x0010U) /*!< dedicated DTCM Ram size selection */
#define OB_USER_SECURITY ((uint32_t)0x0020U) /*!< security selection */
#define OB_USER_SWAP_BANK ((uint32_t)0x0100U) /*!< Bank swap selection */
#define OB_USER_IOHSLV ((uint32_t)0x0200U) /*!< IO HSLV selection */
#define OB_USER_IWDG1_SW ((uint32_t)0x0400U) /*!< Independent watchdog selection */
/**
* @}
*/
/** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP
* @{
*/
#define OB_SECURE_RDP_NOT_ERASE ((uint32_t)0x00000000U) /*!< Secure area is not erased when the RDP level
is decreased from Level 1 to Level 0 or during a mass erase*/
#define OB_SECURE_RDP_ERASE ((uint32_t)FLASH_SCAR_DMES) /*!< Secure area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @{
*/
/**
* @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
* @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
* @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
* @retval The FLASH Boot Base Adress
*/
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
/* Extension Program operation functions *************************************/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);
HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);
HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros
* @{
*/
/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
((RANGE) == FLASH_VOLTAGE_RANGE_4))
#define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \
((VALUE) == OB_WRPSTATE_ENABLE))
#define IS_OPTIONBYTE(VALUE) ((VALUE) <= (OB_USER_IWDG1_SW | OB_USER_NRST_STDBY_D1 | OB_USER_NRST_STOP_D1 |\
OB_USER_IWDG_STOP| OB_USER_IWDG_STDBY | OB_USER_SWAP_BANK |\
OB_USER_ST_RAM_SIZE | OB_USER_SECURITY))
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U)
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || \
((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || \
((LATENCY) == FLASH_LATENCY_7))
#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
(((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \
(((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END)))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFFFFFF00) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
((CONFIG) == OB_PCROP_RDP_ERASE))
#define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
((CONFIG) == OB_SECURE_RDP_ERASE))
#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))
#define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
#define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
#define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
#define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))
#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))
#define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) /*User can only move the security bit from 0 to 1*/
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x400U) && ((TYPE) != 0))
#define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \
((VALUE) == OB_BOOT_ADD1) || \
((VALUE) == OB_BOOT_ADD_BOTH))
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions
* @{
*/
void FLASH_Erase_Sector(uint32_t Sector, uint32_t Bank, uint32_t VoltageRange);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_FLASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_gpio.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_GPIO_H
#define __STM32H7xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup GPIO
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode_define */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull_define */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed_define */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_Alternate_function_selection */
}GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0,
GPIO_PIN_SET
}GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode_define GPIO mode define
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING ((uint32_t)0x11110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x11210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x11310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x11120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x11220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x11320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed_define GPIO speed define
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */
/**
* @}
*/
/** @defgroup GPIO_pull_define GPIO pull define
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Checks whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__: specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending flags.
* @param __EXTI_LINE__: specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
/**
* @brief Checks whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
/**
* @brief Clears the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
/**
* @}
*/
/* Include GPIO HAL Extension module */
#include "stm32h7xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00))
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\
((MODE) == GPIO_MODE_OUTPUT_PP) ||\
((MODE) == GPIO_MODE_OUTPUT_OD) ||\
((MODE) == GPIO_MODE_AF_PP) ||\
((MODE) == GPIO_MODE_AF_OD) ||\
((MODE) == GPIO_MODE_IT_RISING) ||\
((MODE) == GPIO_MODE_IT_FALLING) ||\
((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING) ||\
((MODE) == GPIO_MODE_EVT_FALLING) ||\
((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
((MODE) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW) || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
((PULL) == GPIO_PULLDOWN))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIO_Private_Functions GPIO Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_GPIO_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_GPIO_EX_H
#define __STM32H7xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup GPIOEx GPIOEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_HRTIM1 ((uint8_t)0x01) /* HRTIM1 Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#define GPIO_AF2_HRTIM1 ((uint8_t)0x02) /* HRTIM2 Alternate Function mapping */
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03) /* DFSDM Alternate Function mapping */
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#define GPIO_AF3_LPTIM4 ((uint8_t)0x03) /* LPTIM4 Alternate Function mapping */
#define GPIO_AF3_LPTIM5 ((uint8_t)0x03) /* LPTIM5 Alternate Function mapping */
#define GPIO_AF3_LPUART ((uint8_t)0x03) /* LPUART Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#define GPIO_AF4_DFSDM1 ((uint8_t)0x04) /* DFSDM Alternate Function mapping */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_SAI3 ((uint8_t)0x06) /* SAI3 Alternate Function mapping */
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06) /* DFSDM Alternate Function mapping */
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
#define GPIO_AF7_DFSDM1 ((uint8_t)0x07) /* DFSDM Alternate Function mapping */
#define GPIO_AF7_SDIO1 ((uint8_t)0x07) /* SDIO1 Alternate Function mapping */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define GPIO_AF8_SAI4 ((uint8_t)0x08) /* SAI4 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIF ((uint8_t)0x08) /* SPDIF Alternate Function mapping */
#define GPIO_AF8_LPUART ((uint8_t)0x08) /* LPUART Alternate Function mapping */
#define GPIO_AF8_SDIO1 ((uint8_t)0x08) /* SDIO1 Alternate Function mapping */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#define GPIO_AF9_SDIO2 ((uint8_t)0x09) /* SDIO2 Alternate Function mapping */
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LTDC Alternate Function mapping */
#define GPIO_AF9_SPDIF ((uint8_t)0x09) /* SPDIF Alternate Function mapping */
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#define GPIO_AF9_SAI4 ((uint8_t)0x09) /* SAI4 Alternate Function mapping */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define GPIO_AF10_SAI4 ((uint8_t)0xA) /* SAI4 Alternate Function mapping */
#define GPIO_AF10_SDIO2 ((uint8_t)0xA) /* SDIO2 Alternate Function mapping */
#define GPIO_AF10_OTG2_HS ((uint8_t)0xA) /* OTG2_HS Alternate Function mapping */
#define GPIO_AF10_OTG1_FS ((uint8_t)0xA) /* OTG1_FS Alternate Function mapping */
#define GPIO_AF10_COMP1 ((uint8_t)0xA) /* COMP1 Alternate Function mapping */
#define GPIO_AF10_COMP2 ((uint8_t)0xA) /* COMP2 Alternate Function mapping */
#define GPIO_AF10_LTDC ((uint8_t)0xA) /* LTDC Alternate Function mapping */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_SWP ((uint8_t)0x0B) /* SWP Alternate Function mapping */
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#define GPIO_AF11_MDIOS ((uint8_t)0x0B) /* MDIOS Alternate Function mapping */
#define GPIO_AF11_OTG1_HS ((uint8_t)0x0B) /* OTG1_HS Alternate Function mapping */
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#define GPIO_AF11_SDIO2 ((uint8_t)0x0B) /* SDIO2 Alternate Function mapping */
#define GPIO_AF11_DFSDM1 ((uint8_t)0x0B) /* DFSDM Alternate Function mapping */
#define GPIO_AF11_COMP1 ((uint8_t)0x0B) /* COMP1 Alternate Function mapping */
#define GPIO_AF11_COMP2 ((uint8_t)0x0B) /* COMP2 Alternate Function mapping */
#define GPIO_AF11_I2C4 ((uint8_t)0x0B) /* I2C4 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#define GPIO_AF12_SDIO1 ((uint8_t)0xC) /* SDIO1 Alternate Function mapping */
#define GPIO_AF12_MDIOS ((uint8_t)0xC) /* MDIOS Alternate Function mapping */
#define GPIO_AF12_OTG2_FS ((uint8_t)0xC) /* OTG2_FS Alternate Function mapping */
#define GPIO_AF12_COMP1 ((uint8_t)0xC) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_COMP2 ((uint8_t)0xC) /* COMP2 Alternate Function mapping */
#define GPIO_AF12_LTDC ((uint8_t)0xC) /* LTDC Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_DSI ((uint8_t)0x0D) /* DSI Alternate Function mapping */
#define GPIO_AF13_COMP1 ((uint8_t)0x0D) /* COMP1 Alternate Function mapping */
#define GPIO_AF13_COMP2 ((uint8_t)0x0D) /* COMP2 Alternate Function mapping */
#define GPIO_AF13_LTDC ((uint8_t)0x0D) /* LTDC Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LTDC Alternate Function mapping */
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
* @{
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
* @{
*/
/**
* @brief GPIO pin available on the platform
*/
/* Defines the available pins per GPIOs */
#define GPIOA_PIN_AVAILABLE GPIO_PIN_All
#define GPIOB_PIN_AVAILABLE GPIO_PIN_All
#define GPIOC_PIN_AVAILABLE GPIO_PIN_All
#define GPIOD_PIN_AVAILABLE GPIO_PIN_All
#define GPIOE_PIN_AVAILABLE GPIO_PIN_All
#define GPIOF_PIN_AVAILABLE GPIO_PIN_All
#define GPIOG_PIN_AVAILABLE GPIO_PIN_All
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
* @{
*/
/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
* @{
*/
#define GPIO_GET_INDEX(__GPIOx__) (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
((__GPIOx__) == (GPIOB))? 1U :\
((__GPIOx__) == (GPIOC))? 2U :\
((__GPIOx__) == (GPIOD))? 3U :\
((__GPIOx__) == (GPIOE))? 4U :\
((__GPIOx__) == (GPIOF))? 5U :\
((__GPIOx__) == (GPIOG))? 6U :\
((__GPIOx__) == (GPIOH))? 7U :\
((__GPIOx__) == (GPIOI))? 8U :\
((__GPIOx__) == (GPIOJ))? 9U : 10U)
/**
* @}
*/
#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \
((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOF) && (((__PIN__) & (GPIOF_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOF_PIN_AVAILABLE)) == (GPIOF_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOG) && (((__PIN__) & (GPIOG_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOG_PIN_AVAILABLE)) == (GPIOG_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOI) && (((__PIN__) & (GPIOI_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOI_PIN_AVAILABLE)) == (GPIOI_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOJ) && (((__PIN__) & (GPIOJ_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOJ_PIN_AVAILABLE)) == (GPIOJ_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOK) && (((__PIN__) & (GPIOK_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOK_PIN_AVAILABLE)) == (GPIOK_PIN_AVAILABLE))) || \
(((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE))))
/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
* @{
*/
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_GPIO_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h
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@@ -0,0 +1,579 @@
/**
******************************************************************************
* @file stm32h7xx_hal_hash.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_HASH_H
#define __STM32H7xx_HAL_HASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (HASH)
/** @addtogroup HASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HASH_Exported_Types HASH Exported Types
* @{
*/
/**
* @brief HASH Configuration Structure definition
*/
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.
This parameter can be a value of @ref HASH_Data_Type. */
uint32_t KeySize; /*!< The key size is used only in HMAC operation. */
uint8_t* pKey; /*!< The key is used only in HMAC operation. */
} HASH_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_HASH_STATE_RESET = 0x00, /*!< Peripheral is not initialized */
HAL_HASH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_HASH_STATE_BUSY = 0x02, /*!< Processing (hashing) is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x06, /*!< Timeout state */
HAL_HASH_STATE_ERROR = 0x07, /*!< Error state */
HAL_HASH_STATE_SUSPENDED = 0x08 /*!< Suspended state */
}HAL_HASH_StateTypeDef;
/**
* @brief HAL phase structures definition
*/
typedef enum
{
HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready to start */
HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in HASH processing phase */
HAL_HASH_PHASE_HMAC_STEP_1 = 0x03, /*!< HASH peripheral is in HMAC step 1 processing phase
(step 1 consists in entering the inner hash function key) */
HAL_HASH_PHASE_HMAC_STEP_2 = 0x04, /*!< HASH peripheral is in HMAC step 2 processing phase
(step 2 consists in entering the message text) */
HAL_HASH_PHASE_HMAC_STEP_3 = 0x05 /*!< HASH peripheral is in HMAC step 3 processing phase
(step 3 consists in entering the outer hash function key) */
}HAL_HASH_PhaseTypeDef;
/**
* @brief HAL HASH mode suspend definitions
*/
typedef enum
{
HAL_HASH_SUSPEND_NONE = 0x00, /*!< HASH peripheral suspension not requested */
HAL_HASH_SUSPEND = 0x01 /*!< HASH peripheral suspension is requested */
}HAL_HASH_SuspendTypeDef;
/**
* @brief HASH Handle Structure definition
*/
typedef struct
{
HASH_InitTypeDef Init; /*!< HASH required parameters */
uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */
uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */
uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */
uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */
uint32_t HashBuffSize; /*!< Size of buffer to be processed */
__IO uint32_t HashInCount; /*!< Counter of inputted data */
__IO uint32_t HashITCounter; /*!< Counter of issued interrupts */
__IO uint32_t HashKeyCount; /*!< Counter for Key inputted data (HMAC only) */
HAL_StatusTypeDef Status; /*!< HASH peripheral status */
HAL_HASH_PhaseTypeDef Phase; /*!< HASH peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< HASH In DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_HASH_StateTypeDef State; /*!< HASH peripheral state */
HAL_HASH_SuspendTypeDef SuspendRequest; /*!< HASH peripheral suspension request flag */
FlagStatus DigestCalculationDisable; /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */
} HASH_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HASH_Exported_Constants HASH Exported Constants
* @{
*/
/** @defgroup HASH_Algo_Selection HASH algorithm selection
* @{
*/
#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
/**
* @}
*/
/** @defgroup HASH_Algorithm_Mode HASH algorithm mode
* @{
*/
#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
*/
/** @defgroup HASH_Data_Type HASH input data type
* @{
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
/**
* @}
*/
/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode HMAC key length type
* @{
*/
#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key size is <= 64 bytes */
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key size is > 64 bytes */
/**
* @}
*/
/** @defgroup HASH_flags_definition HASH flags definitions
* @{
*/
#define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
#define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
#define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
#define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy, processing a block of data */
#define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : the input buffer contains at least one word of data */
/**
* @}
*/
/** @defgroup HASH_interrupts_definition HASH interrupts definitions
* @{
*/
#define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */
#define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */
/**
* @}
*/
/** @defgroup HASH_alias HASH API alias
* @{
*/
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HASH_Exported_Macros HASH Exported Macros
* @{
*/
/** @brief Check whether or not the specified HASH flag is set.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete.
* @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.
* @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.
* @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_HASH_GET_FLAG(__FLAG__) (((__FLAG__) > 8U) ? \
((HASH->CR & (__FLAG__)) == (__FLAG__)) :\
((HASH->SR & (__FLAG__)) == (__FLAG__)) )
/** @brief Clear the specified HASH flag.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
* @arg @ref HASH_FLAG_DCIS Digest calculation complete
* @retval None
*/
#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))
/** @brief Enable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
* @retval None
*/
#define __HAL_HASH_ENABLE_IT(__INTERRUPT__) SET_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Disable the specified HASH interrupt.
* @param __INTERRUPT__: specifies the HASH interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref HASH_IT_DINI A new block can be entered into the input buffer (DIN)
* @arg @ref HASH_IT_DCI Digest calculation complete
* @retval None
*/
#define __HAL_HASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
/** @brief Reset HASH handle state.
* @param __HANDLE__: HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
/** @brief Reset HASH handle status.
* @param __HANDLE__: HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
/**
* @brief Enable the multi-buffer DMA transfer mode.
* @note This bit is set when hashing large files when multiple DMA transfers are needed.
* @retval None
*/
#define __HAL_HASH_SET_MDMAT() SET_BIT(HASH->CR, HASH_CR_MDMAT)
/**
* @brief Disable the multi-buffer DMA transfer mode.
* @retval None
*/
#define __HAL_HASH_RESET_MDMAT() CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)
/**
* @brief Start the digest computation.
* @retval None
*/
#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL)
/**
* @brief Set the number of valid bits in the last word written in data register DIN.
* @param __SIZE__: size in bytes of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8 * ((__SIZE__) % 4))
/**
* @brief Reset the HASH core.
* @retval None
*/
#define __HAL_HASH_INIT() SET_BIT(HASH->CR, HASH_CR_INIT)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup HASH_Private_Macros HASH Private Macros
* @{
*/
/**
* @brief Return digest length in bytes.
* @retval Digest length
*/
#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1) ? 20 : \
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ? 28 : \
((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ? 32 : 16 ) ) )
/**
* @brief Return number of words already pushed in the FIFO.
* @retval Number of words already pushed in the FIFO
*/
#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8)
/**
* @brief Ensure that HASH input data type is valid.
* @param __DATATYPE__: HASH input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
((__DATATYPE__) == HASH_DATATYPE_16B)|| \
((__DATATYPE__) == HASH_DATATYPE_8B) || \
((__DATATYPE__) == HASH_DATATYPE_1B))
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in polling mode.
* @note This check is valid only for multi-buffer HASH processing in polling mode.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__) (((__SIZE__) % 4) == 0)
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HASH
* processing in DMA mode.
* @note This check is valid only for multi-buffer HASH processing in DMA mode.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__) ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == RESET) || (((__SIZE__) % 4) == 0))
/**
* @brief Ensure that input data buffer size is valid for multi-buffer HMAC
* processing in DMA mode.
* @note This check is valid only for multi-buffer HMAC processing in DMA mode.
* @param __HANDLE__: HASH handle.
* @param __SIZE__: input data buffer size.
* @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
*/
#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__) ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4) == 0))
/**
* @brief Ensure that handle phase is set to HASH processing.
* @param __HANDLE__: HASH handle.
* @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
*/
#define IS_HASH_PROCESSING(__HANDLE__) ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
/**
* @brief Ensure that handle phase is set to HMAC processing.
* @param __HANDLE__: HASH handle.
* @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
*/
#define IS_HMAC_PROCESSING(__HANDLE__) (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \
((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))
/**
* @}
*/
/* Include HASH HAL Extended module */
#include "stm32h7xx_hal_hash_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HASH_Exported_Functions HASH Exported Functions
* @{
*/
/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization methods **********************************/
HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);
void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);
void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode
* @{
*/
/* HASH processing using polling *********************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode
* @{
*/
/* HASH processing using IT **************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode
* @{
*/
/* HASH processing using DMA *************************************************/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode
* @{
*/
/* HASH-MAC processing using polling *****************************************/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode
* @{
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode
* @{
*/
/* HASH-HMAC processing using DMA ********************************************/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions
* @{
*/
/* Peripheral State methods **************************************************/
HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);
void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);
void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);
/**
* @}
*/
/**
* @}
*/
/* Private functions -----------------------------------------------------------*/
/** @addtogroup HASH_Private_Functions HASH Private Functions
* @{
*/
/* Private functions */
HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
/**
* @}
*/
/**
* @}
*/
#endif /* HASH */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_HASH_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_HASH_EX_H
#define __STM32H7xx_HAL_HASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (HASH)
/** @addtogroup HASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions
* @{
*/
/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode
* @{
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode
* @{
*/
HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HASH */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_HASH_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hcd.h
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/**
******************************************************************************
* @file stm32h7xx_hal_hcd.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_HCD_H
#define __STM32H7xx_HAL_HCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_usb.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Types HCD Exported Types
* @{
*/
/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
* @{
*/
typedef enum
{
HAL_HCD_STATE_RESET = 0x00U,
HAL_HCD_STATE_READY = 0x01U,
HAL_HCD_STATE_ERROR = 0x02U,
HAL_HCD_STATE_BUSY = 0x03U,
HAL_HCD_STATE_TIMEOUT = 0x04U
} HCD_StateTypeDef;
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
/**
* @}
*/
/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
* @{
*/
typedef struct
{
HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
__IO HCD_StateTypeDef State; /*!< HCD communication state */
void *pData; /*!< Pointer Stack Handler */
} HCD_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HCD_Exported_Constants HCD Exported Constants
* @{
*/
/** @defgroup HCD_Speed HCD Speed
* @{
*/
#define HCD_SPEED_HIGH 0U
#define HCD_SPEED_LOW 2U
#define HCD_SPEED_FULL 3U
/**
* @}
*/
/** @defgroup HCD_PHY_Module HCD PHY Module
* @{
*/
#define HCD_PHY_ULPI 1U
#define HCD_PHY_EMBEDDED 2U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Macros HCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_HCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HCD_Exported_Functions HCD Exported Functions
* @{
*/
/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);
void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);
void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/* I/O operation functions ***************************************************/
/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
uint8_t pipe,
uint8_t direction ,
uint8_t ep_type,
uint8_t token,
uint8_t* pbuff,
uint16_t length,
uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
uint8_t chnum,
HCD_URBStateTypeDef urb_state);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup HCD_Private_Macros HCD Private Macros
* @{
*/
/** @defgroup HCD_Instance_definition HCD Instance definition
* @{
*/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB2_OTG_FS) || \
((INSTANCE) == USB1_OTG_HS))
/**
* @}
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HCD_Private_Functions HCD Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_HCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h
+3642
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hsem.h
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/**
******************************************************************************
* @file stm32h7xx_hal_hsem.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of HSEM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_HSEM_H
#define __STM32H7xx_HAL_HSEM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup HSEM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HSEM_Exported_Types HSEM Exported Types
* @{
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HSEM_Exported_Constants HSEM Exported Constants
* @{
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HSEM_Exported_Macros HSEM Exported Macros
* @{
*/
/**
* @brief SemID to mask helper Macro.
* @param __SEMID__: semaphore ID from 0 to 31
* @retval Semaphore Mask.
*/
#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))
/**
* @brief Enables the specified HSEM interrupts.
* @param __SEM_MASK__: semaphores Mask
* @retval None.
*/
#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))
/**
* @brief Disables the specified HSEM interrupts.
* @param __SEM_MASK__: semaphores Mask
* @retval None.
*/
#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))
/**
* @brief Checks whether interrupt has occurred or not for semaphores specified by a mask.
* @param __SEM_MASK__: semaphores Mask
* @retval semaphores Mask : Semaphores where an interrupt occurred.
*/
#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)
/**
* @brief Get the semaphores release status flags.
* @param __SEM_MASK__: semaphores Mask
* @retval semaphores Mask : Semaphores where Release flags rise.
*/
#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)
/**
* @brief Clears the HSEM Interrupt flags.
* @param __SEM_MASK__: semaphores Mask
* @retval None.
*/
#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HSEM_Exported_Functions HSEM Exported Functions
* @{
*/
/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions
* @brief HSEM Take and Release functions
* @{
*/
/* HSEM semaphore take (lock) using 2-Step method ****************************/
HAL_StatusTypeDef HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);
/* HSEM semaphore fast take (lock) using 1-Step method ***********************/
HAL_StatusTypeDef HAL_HSEM_FastTake(uint32_t SemID);
/* HSEM Check semaphore state Taken or not **********************************/
uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);
/* HSEM Release **************************************************************/
void HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);
/* HSEM Release All************************************************************/
void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t MasterID);
/**
* @}
*/
/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions
* @brief HSEM Set and Get Key functions.
* @{
*/
/* HSEM Set Clear Key *********************************************************/
void HAL_HSEM_SetClearKey(uint32_t Key);
/* HSEM Get Clear Key *********************************************************/
uint32_t HAL_HSEM_GetClearKey(void);
/**
* @}
*/
/** @addtogroup HSEM_Exported_Functions_Group3
* @brief HSEM Notification functions
* @{
*/
/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/
void HAL_HSEM_ActivateNotification(uint32_t SemMask);
/* HSEM Deactivate HSEM Notification (When a semaphore is released) ****************/
void HAL_HSEM_DeactivateNotification(uint32_t SemMask);
/* HSEM Free Callback (When a semaphore is released) *******************************/
void HAL_HSEM_FreeCallback(uint32_t SemMask);
/* HSEM IRQ Handler **********************************************************/
void HAL_HSEM_IRQHandler(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup HSEM_Private_Types HSEM Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup HSEM_Private_Variables HSEM Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup HSEM_Private_Constants HSEM Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup HSEM_Private_Macros HSEM Private Macros
* @{
*/
#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )
#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )
#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )
#define IS_HSEM_MASTERID(__MASTERID__) (((__MASTERID__) == HSEM_CM7_MASTERID))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_HSEM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c.h
+675
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/**
******************************************************************************
* @file stm32h7xx_hal_i2c.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_I2C_H
#define __STM32H7xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization
section in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
}I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
}HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
}I2C_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_NO_OPTION_FRAME (0xFFFF0000U)
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XferDirection I2C Transfer Direction
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__: specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32h7xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32h7xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2c_ex.h
+198
View File
@@ -0,0 +1,198 @@
/**
******************************************************************************
* @file stm32h7xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_I2C_EX_H
#define __STM32H7xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP
#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMCR_I2C1_FMP
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMCR_I2C2_FMP
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMCR_I2C3_FMP
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMCR_I2C4_FMP
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#if defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
#elif defined(SYSCFG_PMCR_I2C1_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_I2C_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h
+617
View File
@@ -0,0 +1,617 @@
/**
******************************************************************************
* @file stm32h7xx_hal_i2s.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_I2S_H
#define __STM32H7xx_HAL_I2S_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup I2S
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref I2S_MSB_LSB_transmission */
uint32_t WSInversion; /*!< Control the Word Select Inversion.
This parameter can be a value of @ref I2S_WSInversion */
uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
This parameter can be a value of @ref I2S_IO_Swap */
uint32_t Data24BitAlignment; /*!< Specifies the Data Padding for 24 bits data lenght
This parameter can be a value of @ref I2S_Data_24Bit_Alignment */
uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref I2S_Fifo_Threshold */
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
This parameter can be a value of @ref I2S_Master_Keep_IO_State */
uint32_t SlaveExtendFREDetection; /*!< Control the channel length in SLAVE.
This parameter can be a value of @ref I2S_SlaveExtendFREDetection */
}I2S_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
}HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
typedef struct __I2S_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter */
void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code */
}I2S_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/**
* @defgroup I2S_Error_Defintion I2S Error Defintion
* @brief I2S Error Code
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_UDR (0x00000001U) /*!< I2S Underrun error */
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< I2S Overrun error */
#define HAL_I2S_ERROR_FRE (0x00000004U) /*!< I2S Frame format error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000010U) /*!< Timeout error */
#define HAL_I2S_ERROR_PRESCALER (0x00000020U) /*!< Prescaler error */
/**
* @}
*/
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
#define I2S_MODE_SLAVE_RX (0x00000002U)
#define I2S_MODE_MASTER_TX (0x00000004U)
#define I2S_MODE_MASTER_RX (0x00000006U)
#define I2S_MODE_SLAVE_FD (0x00000008U)
#define I2S_MODE_MASTER_FD (0x0000000AU)
/**
* @}
*/
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
#define I2S_STANDARD_MSB (0x00000010U)
#define I2S_STANDARD_LSB (0x00000020U)
#define I2S_STANDARD_PCM_SHORT (0x00000030U)
#define I2S_STANDARD_PCM_LONG (0x000000B0U)
/**
* @}
*/
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED (0x00000400U)
#define I2S_DATAFORMAT_24B (0x00000500U)
#define I2S_DATAFORMAT_32B (0x00000600U)
/**
* @}
*/
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE SPI_I2SCFGR_MCKOE
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K (192000U)
#define I2S_AUDIOFREQ_96K (96000U)
#define I2S_AUDIOFREQ_48K (48000U)
#define I2S_AUDIOFREQ_44K (44100U)
#define I2S_AUDIOFREQ_32K (32000U)
#define I2S_AUDIOFREQ_22K (22050U)
#define I2S_AUDIOFREQ_16K (16000U)
#define I2S_AUDIOFREQ_11K (11025U)
#define I2S_AUDIOFREQ_8K (8000U)
#define I2S_AUDIOFREQ_DEFAULT (2U)
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW (0x00000000U)
#define I2S_CPOL_HIGH SPI_I2SCFGR_CKPOL
/**
* @}
*/
/** @defgroup I2S_MSB_LSB_transmission I2S MSB LSB Transmission
* @{
*/
#define I2S_FIRSTBIT_MSB (0x00000000U)
#define I2S_FIRSTBIT_LSB SPI_CFG2_LSBFRST
/**
* @}
*/
/** @defgroup I2S_WSInversion I2S Word Select Inversion
* @{
*/
#define I2S_WS_INVERSION_DISABLE (0x00000000U)
#define I2S_WS_INVERSION_ENABLE SPI_I2SCFGR_WSINV
/**
* @}
*/
/** @defgroup I2S_IO_Swap Control I2S IO Swap
* @{
*/
#define I2S_IO_SWAP_DISABLE (0x00000000U)
#define I2S_IO_SWAP_ENABLE SPI_CFG2_IOSWP
/**
* @}
*/
/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit
* @{
*/
#define I2S_DATA_24BIT_ALIGNMENT_RIGHT (0x00000000U)
#define I2S_DATA_24BIT_ALIGNMENT_LEFT SPI_I2SCFGR_DATFMT
/**
* @}
*/
/** @defgroup I2S_Fifo_Threshold I2S Fifo Threshold
* @{
*/
#define I2S_FIFO_THRESHOLD_01DATA (0x00000000U)
#define I2S_FIFO_THRESHOLD_02DATA (0x00000020U)
#define I2S_FIFO_THRESHOLD_03DATA (0x00000040U)
#define I2S_FIFO_THRESHOLD_04DATA (0x00000060U)
#define I2S_FIFO_THRESHOLD_05DATA (0x00000080U)
#define I2S_FIFO_THRESHOLD_06DATA (0x000000A0U)
#define I2S_FIFO_THRESHOLD_07DATA (0x000000C0U)
#define I2S_FIFO_THRESHOLD_08DATA (0x000000E0U)
/**
* @}
*/
/** @defgroup I2S_Master_Keep_IO_State Keep IO State
* @{
*/
#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define I2S_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
/**
* @}
*/
/** @defgroup I2S_SlaveExtendFREDetection Slave Extend FRE Detection
* @{
*/
#define I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE (0x00000000U)
#define I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE SPI_I2SCFGR_FIXCH
/**
* @}
*/
/** @defgroup I2S_Interrupt_definition I2S Interrupt definition
* @{
*/
#define I2S_IT_TXE SPI_IER_TXPIE
#define I2S_IT_RXNE SPI_IER_RXPIE
#define I2S_IT_ERR (SPI_IER_OVRIE | SPI_IER_UDRIE | SPI_IER_TIFREIE)
/**
* @}
*/
/** @defgroup I2S_Flag_definition I2S Flag definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXP /* I2S status flag: Tx buffer empty flag */
#define I2S_FLAG_RXNE SPI_SR_RXP /* I2S status flag: Rx buffer not empty flag */
#define I2S_FLAG_UDR SPI_SR_UDR /* I2S Error flag: Underrun flag */
#define I2S_FLAG_RXWNE SPI_SR_RXWNE /* I2S RxFIFO Word Not Empty */
#define I2S_FLAG_OVR SPI_SR_OVR /* I2S Error flag: Overrun flag */
#define I2S_FLAG_FRE SPI_SR_TIFRE /* I2S Error flag: TI mode frame format error flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__: specifies the I2S Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__: specifies the I2S Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__: specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__: specifies the I2S Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_TXE : Tx buffer empty flag
* @arg I2S_FLAG_RXNE : Rx buffer not empty flag
* @arg I2S_FLAG_UDR : Underrun flag
* @arg I2S_FLAG_OVR : Overrun flag
* @arg I2S_FLAG_FRE : TI mode frame format error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
/** @brief Clear the I2S FRE pending flag.
* @param __HANDLE__: specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
/* Include I2S HAL Extended module */
#include "stm32h7xx_hal_i2s_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2S_Exported_Functions I2S Exported Functions
* @{
*/
/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @defgroup I2S_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private I2S Private
* @{
*/
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_MASTER_RX) || \
((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_FD_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_MASTER(MODE) (((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_MASTER_RX) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_TX_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_MASTER_TX) || \
((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_RX_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_RX) || \
((MODE) == I2S_MODE_MASTER_RX) || \
((MODE) == I2S_MODE_SLAVE_FD) || \
((MODE) == I2S_MODE_MASTER_FD))
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
((STANDARD) == I2S_STANDARD_MSB) || \
((STANDARD) == I2S_STANDARD_LSB) || \
((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
((STANDARD) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
((FORMAT) == I2S_DATAFORMAT_24B) || \
((FORMAT) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
((FREQ) <= I2S_AUDIOFREQ_192K)) || \
((FREQ) == I2S_AUDIOFREQ_DEFAULT))
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
((CPOL) == I2S_CPOL_HIGH))
#define IS_I2S_FIRST_BIT(FIRSTBIT) (((FIRSTBIT) == I2S_FIRSTBIT_MSB) || \
((FIRSTBIT) == I2S_FIRSTBIT_LSB))
#define IS_I2S_WS_INVERSION(WSINV) (((WSINV) == I2S_WS_INVERSION_DISABLE) || \
((WSINV) == I2S_WS_INVERSION_ENABLE))
#define IS_I2S_IO_SWAP(IOSWAP) (((IOSWAP) == I2S_IO_SWAP_DISABLE) || \
((IOSWAP) == I2S_IO_SWAP_ENABLE))
#define IS_I2S_DATA_24BIT_ALIGNMENT(ALIGNMENT) (((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \
((ALIGNMENT) == I2S_DATA_24BIT_ALIGNMENT_LEFT))
#define IS_I2S_FIFO_THRESHOLD(FTHLV) (((FTHLV) == I2S_FIFO_THRESHOLD_01DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_02DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_03DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_04DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_05DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_06DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_07DATA) || \
((FTHLV) == I2S_FIFO_THRESHOLD_08DATA))
#define IS_I2S_MASTER_KEEP_IO_STATE(AFCNTR) (((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_DISABLE) || \
((AFCNTR) == I2S_MASTER_KEEP_IO_STATE_ENABLE))
#define IS_I2S_SLAVE_EXTEND_FRE_DETECTION(FIXCH) (((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_DISABLE) || \
((FIXCH) == I2S_SLAVE_EXTEND_FRE_DETECTION_ENABLE))
/**
* @}
*/
/* Define the private group ***************************************************/
/******************************************************************************/
/** @defgroup I2S_Private I2S Private
* @{
*/
/**
* @}
*/
/******************************************************************************/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_I2S_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_i2s_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_I2S_EX_H
#define __STM32H7xx_HAL_I2S_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup I2SEx I2SEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
* @{
*/
/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
* @{
*/
/* Extended features functions *************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size);
/* I2S Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_I2S_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h
+850
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/**
******************************************************************************
* @file stm32h7xx_hal_irda.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_IRDA_H
#define __STM32H7xx_HAL_IRDA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup IRDA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
*/
/**
* @brief IRDA Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
The baud rate register is computed using the following formula:
Baud Rate Register = ((PCLKx) / ((hirda->Init.BaudRate))) */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDA_Word_Length */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref IRDA_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
to achieve low-power frequency.
@note Prescaler value 0 is forbidden */
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
This parameter can be a value of @ref IRDA_Low_Power */
}IRDA_InitTypeDef;
/**
* @brief HAL IRDA State structures definition
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_IRDA_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
}HAL_IRDA_StateTypeDef;
/**
* @brief HAL IRDA Error Code structure definition
*/
typedef enum
{
HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */
HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */
HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */
HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */
HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */
HAL_IRDA_ERROR_DMA = 0x10, /*!< DMA transfer error */
HAL_IRDA_ERROR_BUSY = 0x20 /*!< Busy Error */
}HAL_IRDA_ErrorTypeDef;
/**
* @brief IRDA clock sources definition
*/
typedef enum
{
IRDA_CLOCKSOURCE_D2PCLK1 = 0x00, /*!< Domain2 PCLK1 clock source */
IRDA_CLOCKSOURCE_D2PCLK2 = 0x01, /*!< Domain2 PCLK2 clock source */
IRDA_CLOCKSOURCE_D3PCLK1 = 0x02, /*!< Domain3 PCLK1 clock source */
IRDA_CLOCKSOURCE_PLL2Q = 0x04, /*!< PLL2Q clock source */
IRDA_CLOCKSOURCE_HSI = 0x08, /*!< HSI clock source */
IRDA_CLOCKSOURCE_CSI = 0x10, /*!< CSI clock source */
IRDA_CLOCKSOURCE_LSE = 0x20, /*!< LSE clock source */
IRDA_CLOCKSOURCE_PLL3Q = 0x40, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_UNDEFINED = 0x80 /*!< Undefined clock source */
}IRDA_ClockSourceTypeDef;
/**
* @brief IRDA handle Structure definition
*/
typedef struct
{
USART_TypeDef *Instance; /*!< IRDA registers base address */
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
uint16_t Mask; /*!< IRDA RX RDR register mask */
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
uint32_t ErrorCode; /*!< IRDA Error code */
}IRDA_HandleTypeDef;
/**
* @brief IRDA Configuration enumeration values definition
*/
typedef enum
{
IRDA_BAUDRATE = 0x00, /*!< IRDA Baud rate */
IRDA_PARITY = 0x01, /*!< IRDA frame parity */
IRDA_WORDLENGTH = 0x02, /*!< IRDA frame length */
IRDA_MODE = 0x03, /*!< IRDA communication mode */
IRDA_PRESCALER = 0x04, /*!< IRDA prescaling */
IRDA_POWERMODE = 0x05 /*!< IRDA power mode */
}IRDA_ControlTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
* @{
*/
/** @defgroup IRDA_Word_Length IRDA Word Length
* @{
*/
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long frame */
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000) /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long frame */
/**
* @}
*/
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE ((uint32_t)0x00000000) /*!< No parity */
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /*!< Even parity */
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) /*!< Odd parity */
/**
* @}
*/
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
* @{
*/
#define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) /*!< RX mode */
#define IRDA_MODE_TX ((uint32_t)USART_CR1_TE) /*!< TX mode */
#define IRDA_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) /*!< RX and TX mode */
/**
* @}
*/
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x00000000) /*!< IRDA normal power mode */
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP) /*!< IRDA low power mode */
/**
* @}
*/
/** @defgroup IRDA_State IRDA State
* @{
*/
#define IRDA_STATE_DISABLE ((uint32_t)0x00000000) /*!< IRDA disabled */
#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE) /*!< IRDA enabled */
/**
* @}
*/
/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
#define IRDA_MODE_DISABLE ((uint32_t)0x00000000) /*!< Associated UART disabled in IRDA mode */
#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN) /*!< Associated UART enabled in IRDA mode */
/**
* @}
*/
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
* @{
*/
#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /*!< One-bit sampling disabled */
#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /*!< One-bit sampling enabled */
/**
* @}
*/
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA TX disabled */
#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /*!< IRDA DMA TX enabled */
/**
* @}
*/
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
#define IRDA_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< IRDA DMA RX disabled */
#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /*!< IRDA DMA RX enabled */
/**
* @}
*/
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
* @{
*/
#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
/**
* @}
*/
/** @defgroup IRDA_Flags IRDA Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define IRDA_FLAG_REACK ((uint32_t)0x00400000) /*!< IRDA Receive enable acknowledge flag */
#define IRDA_FLAG_TEACK ((uint32_t)0x00200000) /*!< IRDA Transmit enable acknowledge flag */
#define IRDA_FLAG_BUSY ((uint32_t)0x00010000) /*!< IRDA Busy flag */
#define IRDA_FLAG_ABRF ((uint32_t)0x00008000) /*!< IRDA Auto baud rate flag */
#define IRDA_FLAG_ABRE ((uint32_t)0x00004000) /*!< IRDA Auto baud rate error */
#define IRDA_FLAG_TXE ((uint32_t)0x00000080) /*!< IRDA Transmit data register empty */
#define IRDA_FLAG_TC ((uint32_t)0x00000040) /*!< IRDA Transmission complete */
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020) /*!< IRDA Read data register not empty */
#define IRDA_FLAG_ORE ((uint32_t)0x00000008) /*!< IRDA Overrun error */
#define IRDA_FLAG_NE ((uint32_t)0x00000004) /*!< IRDA Noise error */
#define IRDA_FLAG_FE ((uint32_t)0x00000002) /*!< IRDA Framing error */
#define IRDA_FLAG_PE ((uint32_t)0x00000001) /*!< IRDA Parity error */
/**
* @}
*/
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define IRDA_IT_PE ((uint16_t)0x0028) /*!< IRDA Parity error interruption */
#define IRDA_IT_TXE ((uint16_t)0x0727) /*!< IRDA Transmit data register empty interruption */
#define IRDA_IT_TC ((uint16_t)0x0626) /*!< IRDA Transmission complete interruption */
#define IRDA_IT_RXNE ((uint16_t)0x0525) /*!< IRDA Read data register not empty interruption */
#define IRDA_IT_IDLE ((uint16_t)0x0424) /*!< IRDA Idle interruption */
#define IRDA_IT_ERR ((uint16_t)0x0060) /*!< IRDA Error interruption */
#define IRDA_IT_ORE ((uint16_t)0x0300) /*!< IRDA Overrun error interruption */
#define IRDA_IT_NE ((uint16_t)0x0200) /*!< IRDA Noise error interruption */
#define IRDA_IT_FE ((uint16_t)0x0100) /*!< IRDA Frame error interruption */
/**
* @}
*/
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
* @{
*/
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
/**
* @}
*/
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
* @{
*/
#define IRDA_IT_MASK ((uint16_t)0x001F) /*!< IRDA Interruptions flags mask */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
* @{
*/
/** @brief Reset IRDA handle state.
* @param __HANDLE__: IRDA handle.
* @retval None
*/
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
} while(0)
/** @brief Flush the IRDA DR register.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref IRDA_CLEAR_PEF
* @arg @ref IRDA_CLEAR_FEF
* @arg @ref IRDA_CLEAR_NEF
* @arg @ref IRDA_CLEAR_OREF
* @arg @ref IRDA_CLEAR_TCF
* @arg @ref IRDA_CLEAR_IDLEF
* @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the IRDA PE pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
/** @brief Clear the IRDA FE pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
/** @brief Clear the IRDA NE pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
/** @brief Clear the IRDA ORE pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
/** @brief Clear the IRDA IDLE pending flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref IRDA_FLAG_BUSY Busy flag
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
* @arg @ref IRDA_FLAG_NE Noise Error flag
* @arg @ref IRDA_FLAG_FE Framing Error flag
* @arg @ref IRDA_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __IT__: specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
* @arg @ref IRDA_IT_NE Noise Error interrupt
* @arg @ref IRDA_IT_FE Framing Error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08)))
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __IT__: specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific IRDA request flag.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __REQ__: specifies the request flag to set
* This parameter can be one of the following values:
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the IRDA one bit sample method.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the IRDA one bit sample method.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART/USART associated to IRDA Handle.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup IRDA_Private_Macros IRDA Private Macros
* @{
*/
/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @param __HANDLE__: specifies the IRDA Handle.
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FF ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007F ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007F ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003F ; \
} \
} \
} while(0)
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
* @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
* @retval True or False
*/
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
* @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
* @retval True or False
*/
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
/**
* @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__: IRDA frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
/**
* @brief Ensure that IRDA frame parity is valid.
* @param __PARITY__: IRDA frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
((__PARITY__) == IRDA_PARITY_EVEN) || \
((__PARITY__) == IRDA_PARITY_ODD))
/**
* @brief Ensure that IRDA communication mode is valid.
* @param __MODE__: IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
/**
* @brief Ensure that IRDA power mode is valid.
* @param __MODE__: IRDA power mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
((__MODE__) == IRDA_POWERMODE_NORMAL))
/**
* @brief Ensure that IRDA state is valid.
* @param __STATE__: IRDA state mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
((__STATE__) == IRDA_STATE_ENABLE))
/**
* @brief Ensure that IRDA associated UART/USART mode is valid.
* @param __MODE__: IRDA associated UART/USART mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
((__MODE__) == IRDA_MODE_ENABLE))
/**
* @brief Ensure that IRDA sampling rate is valid.
* @param __ONEBIT__: IRDA sampling rate.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
*/
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
/**
* @brief Ensure that IRDA DMA TX mode is valid.
* @param __DMATX__: IRDA DMA TX mode.
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
*/
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
((__DMATX__) == IRDA_DMA_TX_ENABLE))
/**
* @brief Ensure that IRDA DMA RX mode is valid.
* @param __DMARX__: IRDA DMA RX mode.
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
*/
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
((__DMARX__) == IRDA_DMA_RX_ENABLE))
/**
* @brief Ensure that IRDA request is valid.
* @param __PARAM__: IRDA request.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
/* Include IRDA HAL Extended module */
#include "stm32h7xx_hal_irda_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
* @{
*/
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortCpltCallback (IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortTransmitCpltCallback (IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortReceiveCpltCallback (IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_IRDA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h
+289
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/**
******************************************************************************
* @file stm32h7xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_IRDA_EX_H
#define __STM32H7xx_HAL_IRDA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup IRDAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
* @{
*/
/** @brief Report the IRDA clock source.
* @param __HANDLE__: specifies the IRDA Handle.
* @param __CLOCKSOURCE__: output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART2CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART2CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART3CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART3CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART4CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART4CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART5CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART5CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART6CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART6CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART7) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
case RCC_UART7CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART7CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART7CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART7CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART7CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART7CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART8) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
case RCC_UART8CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART8CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_UART8CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_UART8CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART8CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI; \
break; \
case RCC_UART8CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
} \
} \
} while(0)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_IRDA_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_iwdg.h
+257
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/**
******************************************************************************
* @file stm32h7xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_IWDG_H
#define __STM32H7xx_HAL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup IWDG IWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{
*/
/**
* @brief IWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
} IWDG_InitTypeDef;
/**
* @brief IWDG Handle Structure definition
*/
typedef struct
{
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
}IWDG_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
/** @defgroup IWDG_Window_option IWDG Window option
* @{
*/
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{
*/
/**
* @brief Enable the IWDG peripheral.
* @param __HANDLE__: IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
* @param __HANDLE__: IWDG handle
* @retval None
*/
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{
*/
/* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{
*/
/**
* @brief IWDG Key Register BitMask
*/
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__: IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__: IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Check IWDG prescaler value.
* @param __PRESCALER__: IWDG prescaler value
* @retval None
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/**
* @brief Check IWDG reload value.
* @param __RELOAD__: IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @brief Check IWDG window value.
* @param __WINDOW__: IWDG window value
* @retval None
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_IWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_jpeg.h
+572
View File
@@ -0,0 +1,572 @@
/**
******************************************************************************
* @file stm32h7xx_hal_jpeg.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of JPEG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_JPEG_H
#define __STM32H7xx_HAL_JPEG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_mdma.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup JPEG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup JPEG_Exported_Types JPEG Exported Types
* @{
*/
/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
* @brief JPEG encoding configuration Structure definition
* @{
*/
typedef struct
{
uint8_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
This parameter can be a value of @ref JPEG_ColorSpace */
uint8_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
This parameter can be a value of @ref JPEG_ChromaSubsampling */
uint32_t ImageHeight; /*!< Image height : number of lines */
uint32_t ImageWidth; /*!< Image width : number of pixels per line */
uint8_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */
}JPEG_ConfTypeDef;
/**
* @}
*/
/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
* @brief HAL JPEG State structure definition
* @{
*/
typedef enum
{
HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */
HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */
HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */
HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */
HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */
HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */
}HAL_JPEG_STATETypeDef;
/**
* @}
*/
/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
* @brief JPEG handle Structure definition
* @{
*/
typedef struct
{
JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */
JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */
uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
__IO uint32_t JpegInCount; /*!< Internal Counter of input data */
__IO uint32_t JpegOutCount; /*!< Internal Counter of output data */
uint32_t InDataLength; /*!< Input Buffer Length in Bytes */
uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */
MDMA_HandleTypeDef *hdmain; /*!< JPEG In MDMA handle parameters */
MDMA_HandleTypeDef *hdmaout; /*!< JPEG Out MDMA handle parameters */
uint8_t CustomQuanTable; /*!< If set to 1 specify that user customized quantization tables are used */
uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */
uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */
uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */
uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */
HAL_LockTypeDef Lock; /*!< JPEG locking object */
__IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */
__IO uint32_t ErrorCode; /*!< JPEG Error code */
__IO uint32_t Context; /*!< JPEG Internal context */
}JPEG_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup JPEG_Exported_Constants JPEG Exported Constants
* @{
*/
/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
* @brief JPEG Error Code definition
* @{
*/
#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */
#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */
#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */
/**
* @}
*/
/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
* @brief JPEG Quantization Table Size
* @{
*/
#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes */
/**
* @}
*/
/** @defgroup JPEG_ColorSpace JPEG ColorSpace
* @brief JPEG Color Space
* @{
*/
#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE
/**
* @}
*/
/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling
* @brief JPEG Chrominance Sampling
* @{
*/
#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */
#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */
#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */
/**
* @}
*/
/** @defgroup JPEG_ImageQuality JPEG Image Quality
* @brief JPEG Min and Max Image Quality
* @{
*/
#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */
#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */
/**
* @}
*/
/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
* @brief JPEG Interrupt definition
* @{
*/
#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */
#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */
#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */
#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */
#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */
#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */
/**
* @}
*/
/** @defgroup JPEG_Flag_definition JPEG Flag definition
* @brief JPEG Flags definition
* @{
*/
#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */
#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */
#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */
#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */
#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/
#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/
/**
* @}
*/
/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
* @brief JPEG process pause, resume definition
* @{
*/
#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/
#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/
#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup JPEG_Exported_Macros JPEG Exported Macros
* @{
*/
/** @brief Reset JPEG handle state
* @param __HANDLE__: specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
/**
* @brief Enable the JPEG peripheral.
* @param __HANDLE__: specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
/**
* @brief Disable the JPEG peripheral.
* @param __HANDLE__: specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
/**
* @brief Check the specified JPEG status flag.
* @param __HANDLE__: specifies the JPEG handle.
* @param __FLAG__ : specifies the flag to check
* This parameter can be one of the following values:
* @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
* @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
* @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
* @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
* and than last data has been sent to the output FIFO
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
* and the internal registers have been updated
* @arg JPEG_FLAG_COF : JPEG Codec operation on going flag
*
* @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
*/
#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
/**
* @brief Clear the specified JPEG status flag.
* @param __HANDLE__: specifies the JPEG handle.
* @param __FLAG__ : specifies the flag to clear
* This parameter can be one of the following values:
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
* and than last data has been sent to the output FIFO
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
* @retval : None
*/
#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
/**
* @brief Enable Interrupt.
* @param __HANDLE__: specifies the JPEG handle.
* @param __INTERRUPT__ : specifies the interrupt to enable
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @retval : No retrun
*/
#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
/**
* @brief Disable Interrupt.
* @param __HANDLE__: specifies the JPEG handle.
* @param __INTERRUPT__ : specifies the interrupt to disable
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @note : To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
* located in the same IT enable register (CR register).
* @retval : No retrun
*/
#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
/**
* @brief Get Interrupt state.
* @param __HANDLE__: specifies the JPEG handle.
* @param __INTERRUPT__ : specifies the interrupt to check
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @retval : returns The new state of __INTERRUPT__ (Enabled or disabled)
*/
#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup JPEG_Exported_Functions
* @{
*/
/** @addtogroup JPEG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group2
* @{
*/
/* Encoding/Decoding Configuration functions ********************************/
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group3
* @{
*/
/* JPEG processing functions **************************************/
HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout);
HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group4
* @{
*/
/* JPEG Decode/Encode callback functions ********************************************************/
void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo);
void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group5
* @{
*/
/* JPEG IRQ handler management ******************************************************/
void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group6
* @{
*/
/* Peripheral State and Error functions ************************************************/
HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);
uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup JPEG_Private_Types JPEG Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup JPEG_Private_Defines JPEG Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Variables JPEG Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Constants JPEG Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup JPEG_Private_Macros JPEG Private Macros
* @{
*/
#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \
((COLORSPACE) == JPEG_CMYK_COLORSPACE))
#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Functions JPEG Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_JPEG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h
+712
View File
@@ -0,0 +1,712 @@
/**
******************************************************************************
* @file stm32h7xx_hal_lptim.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_LPTIM_H
#define __STM32H7xx_HAL_LPTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup LPTIM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
* @{
*/
/**
* @brief LPTIM Clock configuration definition
*/
typedef struct
{
uint32_t Source; /*!< Selects the clock source.
This parameter can be a value of @ref LPTIM_Clock_Source */
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
}LPTIM_ClockConfigTypeDef;
/**
* @brief LPTIM Clock configuration definition
*/
typedef struct
{
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
if the ULPTIM input is selected.
Note: This parameter is used only when Ultra low power clock source is used.
Note: If the polarity is configured on 'both edges', an auxiliary clock
(one of the Low power oscillator) must be active.
This parameter can be a value of @ref LPTIM_Clock_Polarity */
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
Note: This parameter is used only when Ultra low power clock source is used.
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
}LPTIM_ULPClockConfigTypeDef;
/**
* @brief LPTIM Trigger configuration definition
*/
typedef struct
{
uint32_t Source; /*!< Selects the Trigger source.
This parameter can be a value of @ref LPTIM_Trigger_Source */
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
Note: This parameter is used only when an external trigger is used.
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
Note: This parameter is used only when an external trigger is used.
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
}LPTIM_TriggerConfigTypeDef;
/**
* @brief LPTIM Initialization Structure definition
*/
typedef struct
{
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
This parameter can be a value of @ref LPTIM_Output_Polarity */
uint32_t UpdateMode; /*!< Specifies whether the update of the autorelaod and the compare
values is done immediately or after the end of current period.
This parameter can be a value of @ref LPTIM_Updating_Mode */
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
or each external event.
This parameter can be a value of @ref LPTIM_Counter_Source */
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
This parameter can be a value of @ref LPTIM_Input1_Source */
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
Note: This parameter is used only for encoder feature so is used only
for LPTIM1 instance.
This parameter can be a value of @ref LPTIM_Input2_Source */
}LPTIM_InitTypeDef;
/**
* @brief HAL LPTIM State structure definition
*/
typedef enum __HAL_LPTIM_StateTypeDef
{
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
}HAL_LPTIM_StateTypeDef;
/**
* @brief LPTIM handle Structure definition
*/
typedef struct
{
LPTIM_TypeDef *Instance; /*!< Register base address */
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
}LPTIM_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
* @{
*/
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
* @{
*/
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
/**
* @}
*/
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
* @{
*/
#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2))
#define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2))
#define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC)
/**
* @}
*/
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
* @{
*/
#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
/**
* @}
*/
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
* @{
*/
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
/**
* @}
*/
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
* @{
*/
#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
* @}
*/
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
* @{
*/
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL
/**
* @}
*/
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
* @{
*/
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
/**
* @}
*/
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
* @{
*/
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
/**
* @}
*/
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
* @{
*/
#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
/**
* @}
*/
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
* @{
*/
#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
/**
* @}
*/
/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
* @{
*/
#define LPTIM_INPUT1SOURCE_GPIO ((uint32_t)0x00000000U) /*!< For LPTIM1, LPTIM2 and LPTIM3 */
#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_CFGR2_IN1_SEL0 /*!< For LPTIM1 and LPTIM2 */
#define LPTIM_INPUT1SOURCE_COMP2 LPTIM_CFGR2_IN1_SEL1 /*!< For LPTIM2 and LPTIM2 */
#define LPTIM_INPUT1SOURCE_COMP1_COMP2 (LPTIM_CFGR2_IN1_SEL0|LPTIM_CFGR2_IN1_SEL1) /*!< For LPTIM2 */
#define LPTIM_INPUT1SOURCE_SAI1_FSA LPTIM_CFGR2_IN1_SEL0 /*!< For LPTIM3 */
#define LPTIM_INPUT1SOURCE_SAI1_FSB LPTIM_CFGR2_IN1_SEL1 /*!< For LPTIM3 */
/**
* @}
*/
/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
* @{
*/
#define LPTIM_INPUT2SOURCE_GPIO ((uint32_t)0x00000000U) /*!< For LPTIM1 and LPTIM2 */
#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_CFGR2_IN2_SEL0 /*!< For LPTIM1 and LPTIM2 */
/**
* @}
*/
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
* @{
*/
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define LPTIM_FLAG_UP LPTIM_ISR_UP
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
/**
* @}
*/
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
* @{
*/
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define LPTIM_IT_UP LPTIM_IER_UPIE
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
* @{
*/
/** @brief Reset LPTIM handle state
* @param __HANDLE__: LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
/**
* @brief Enable the LPTIM peripheral.
* @param __HANDLE__: LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
/**
* @brief Disable the LPTIM peripheral.
* @param __HANDLE__: LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(LPTIM_CR_ENABLE))
/**
* @brief Start the LPTIM peripheral in Continuous mode.
* @param __HANDLE__: LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
/**
* @brief Start the LPTIM peripheral in single mode.
* @param __HANDLE__: LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
/**
* @brief Reset the LPTIM Counter register in synchronous mode.
* @param __HANDLE__: LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
/**
* @brief Reset after read of the LPTIM Counter register in asynchronous mode.
* @param __HANDLE__: LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
/**
* @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__: LPTIM handle
* @param __VALUE__ : Autoreload value
* @retval None
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
/**
* @brief Write the passed parameter in the Compare register.
* @param __HANDLE__: LPTIM handle
* @param __VALUE__ : Compare value
* @retval None
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
/**
* @brief Check whether the specified LPTIM flag is set or not.
* @param __HANDLE__: LPTIM handle
* @param __FLAG__ : LPTIM flag to check
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @retval The state of the specified flag (SET or RESET).
*/
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified LPTIM flag.
* @param __HANDLE__: LPTIM handle.
* @param __FLAG__ : LPTIM flag to clear.
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @retval None.
*/
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified LPTIM interrupt.
* @param __HANDLE__ : LPTIM handle.
* @param __INTERRUPT__ : LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disable the specified LPTIM interrupt.
* @param __HANDLE__ : LPTIM handle.
* @param __INTERRUPT__ : LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/**
* @brief Check whether the specified LPTIM interrupt is set or not.
* @param __HANDLE__ : LPTIM handle.
* @param __INTERRUPT__ : LPTIM interrupt to check.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval Interrupt status.
*/
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @}
*/
/* End of exported macros ----------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
* @{
*/
/**
* @}
*/
/* End of private constants --------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
* @{
*/
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
((__TRIG__) == LPTIM_TRIGSOURCE_7))
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF)
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF)
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
((((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1))) \
|| \
(((__INSTANCE__) == LPTIM2) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2))) \
|| \
(((__INSTANCE__) == LPTIM3) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSA) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSB))))
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
(((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)) \
|| \
((__INSTANCE__) == LPTIM2) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################# One Pulse Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################## Set once Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################### Encoder Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################# Time out Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################## Counter Mode ###############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
/* CallBack functions ********************************************************/
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_LPTIM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ltdc.h
+676
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@@ -0,0 +1,676 @@
/**
******************************************************************************
* @file stm32h7xx_hal_ltdc.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_LTDC_H
#define __STM32H7xx_HAL_LTDC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup LTDC LTDC
* @brief LTDC HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Types LTDC Exported Types
* @{
*/
#define MAX_LAYER 2U
/**
* @brief LTDC color structure definition
*/
typedef struct
{
uint8_t Blue; /*!< Configures the blue value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Green; /*!< Configures the green value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Red; /*!< Configures the red value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint8_t Reserved; /*!< Reserved 0xFF */
} LTDC_ColorTypeDef;
/**
* @brief LTDC Init structure definition
*/
typedef struct
{
uint32_t HSPolarity; /*!< configures the horizontal synchronization polarity.
This parameter can be one value of @ref LTDC_HS_POLARITY */
uint32_t VSPolarity; /*!< configures the vertical synchronization polarity.
This parameter can be one value of @ref LTDC_VS_POLARITY */
uint32_t DEPolarity; /*!< configures the data enable polarity.
This parameter can be one of value of @ref LTDC_DE_POLARITY */
uint32_t PCPolarity; /*!< configures the pixel clock polarity.
This parameter can be one of value of @ref LTDC_PC_POLARITY */
uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width.
This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */
uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height.
This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */
uint32_t AccumulatedActiveW; /*!< configures the accumulated active width.
This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */
uint32_t AccumulatedActiveH; /*!< configures the accumulated active height.
This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */
uint32_t TotalWidth; /*!< configures the total width.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */
uint32_t TotalHeigh; /*!< configures the total height.
This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */
} LTDC_InitTypeDef;
/**
* @brief LTDC Layer structure definition
*/
typedef struct
{
uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
uint32_t WindowY0; /*!< Configures the Window vertical Start Position.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
uint32_t WindowY1; /*!< Configures the Window vertical Stop Position.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */
uint32_t PixelFormat; /*!< Specifies the pixel format.
This parameter can be one of value of @ref LTDC_Pixelformat */
uint32_t Alpha; /*!< Specifies the constant alpha used for blending.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t Alpha0; /*!< Configures the default alpha value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t BlendingFactor1; /*!< Select the blending factor 1.
This parameter can be one of value of @ref LTDC_BlendingFactor1 */
uint32_t BlendingFactor2; /*!< Select the blending factor 2.
This parameter can be one of value of @ref LTDC_BlendingFactor2 */
uint32_t FBStartAdress; /*!< Configures the color frame buffer address */
uint32_t ImageWidth; /*!< Configures the color frame buffer line length.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */
uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer.
This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */
LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */
} LTDC_LayerCfgTypeDef;
/**
* @brief HAL LTDC State enumeration definition
*/
typedef enum
{
HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
}HAL_LTDC_StateTypeDef;
/**
* @brief LTDC handle Structure definition
*/
typedef struct
{
LTDC_TypeDef *Instance; /*!< LTDC Register base address */
LTDC_InitTypeDef Init; /*!< LTDC parameters */
LTDC_LayerCfgTypeDef LayerCfg[MAX_LAYER]; /*!< LTDC Layers parameters */
HAL_LockTypeDef Lock; /*!< LTDC Lock */
__IO HAL_LTDC_StateTypeDef State; /*!< LTDC state */
__IO uint32_t ErrorCode; /*!< LTDC Error code */
} LTDC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDC_Exported_Constants LTDC Exported Constants
* @{
*/
/** @defgroup LTDC_Error_Code LTDC Error Code
* @{
*/
#define HAL_LTDC_ERROR_NONE (0x00000000U) /*!< LTDC No error */
#define HAL_LTDC_ERROR_TE (0x00000001U) /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU (0x00000002U) /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT (0x00000020U) /*!< LTDC Timeout error */
/**
* @}
*/
/** @defgroup LTDC_Layer LTDC Layer
* @{
*/
#define LTDC_LAYER_1 (0x00000000U) /*!< LTDC Layer 1 */
#define LTDC_LAYER_2 (0x00000001U) /*!< LTDC Layer 2 */
/**
* @}
*/
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{
*/
#define LTDC_HSPOLARITY_AL (0x00000000U) /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{
*/
#define LTDC_VSPOLARITY_AL (0x00000000U) /*!< Vertical Synchronization is active low. */
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
/**
* @}
*/
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
* @{
*/
#define LTDC_DEPOLARITY_AL (0x00000000U) /*!< Data Enable, is active low. */
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/**
* @}
*/
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{
*/
#define LTDC_PCPOLARITY_IPC (0x00000000U) /*!< input pixel clock. */
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/**
* @}
*/
/** @defgroup LTDC_SYNC LTDC SYNC
* @{
*/
#define LTDC_HORIZONTALSYNC (LTDC_SSCR_HSW >> 16) /*!< Horizontal synchronization width. */
#define LTDC_VERTICALSYNC LTDC_SSCR_VSH /*!< Vertical synchronization height. */
/**
* @}
*/
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
* @{
*/
#define LTDC_COLOR (0x000000FFU) /*!< Color mask */
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{
*/
#define LTDC_BLENDING_FACTOR1_CA (0x00000400U) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA (0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{
*/
#define LTDC_BLENDING_FACTOR2_CA (0x00000005U) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA (0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 (0x00000000U) /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 (0x00000001U) /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 (0x00000002U) /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 (0x00000003U) /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 (0x00000004U) /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 (0x00000005U) /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 (0x00000006U) /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 (0x00000007U) /*!< AL88 LTDC pixel format */
/**
* @}
*/
/** @defgroup LTDC_Alpha LTDC Alpha
* @{
*/
#define LTDC_ALPHA LTDC_LxCACR_CONSTA /*!< LTDC Cte Alpha mask */
/**
* @}
*/
/** @defgroup LTDC_LAYER_Config LTDC LAYER Config
* @{
*/
#define LTDC_STOPPOSITION (LTDC_LxWHPCR_WHSPPOS >> 16) /*!< LTDC Layer stop position */
#define LTDC_STARTPOSITION LTDC_LxWHPCR_WHSTPOS /*!< LTDC Layer start position */
#define LTDC_COLOR_FRAME_BUFFER LTDC_LxCFBLR_CFBLL /*!< LTDC Layer Line length */
#define LTDC_LINE_NUMBER LTDC_LxCFBLNR_CFBLNBR /*!< LTDC Layer Line number */
/**
* @}
*/
/** @defgroup LTDC_Interrupts LTDC Interrupts
* @{
*/
#define LTDC_IT_LI LTDC_IER_LIE
#define LTDC_IT_FU LTDC_IER_FUIE
#define LTDC_IT_TE LTDC_IER_TERRIE
#define LTDC_IT_RR LTDC_IER_RRIE
/**
* @}
*/
/** @defgroup LTDC_Flags LTDC Flags
* @{
*/
#define LTDC_FLAG_LI LTDC_ISR_LIF
#define LTDC_FLAG_FU LTDC_ISR_FUIF
#define LTDC_FLAG_TE LTDC_ISR_TERRIF
#define LTDC_FLAG_RR LTDC_ISR_RRIF
/**
* @}
*/
/** @defgroup LTDC_Reload_Type LTDC Reload Type
* @{
*/
#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LTDC_Exported_Macros LTDC Exported Macros
* @{
*/
/** @brief Reset LTDC handle state.
* @param __HANDLE__ LTDC handle
* @retval None
*/
#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)
/**
* @brief Enable the LTDC.
* @param __HANDLE__: LTDC handle
* @retval None.
*/
#define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)
/**
* @brief Disable the LTDC.
* @param __HANDLE__: LTDC handle
* @retval None.
*/
#define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))
/**
* @brief Enable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be enabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)
/**
* @brief Disable the LTDC Layer.
* @param __HANDLE__ LTDC handle
* @param __LAYER__ Specify the layer to be disabled.
* This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).
* @retval None.
*/
#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)
/**
* @brief Reload immediately all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)
/**
* @brief Reload during vertical blanking period all LTDC Layers.
* @param __HANDLE__ LTDC handle
* @retval None.
*/
#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)
/* Interrupt & Flag management */
/**
* @brief Get the LTDC pending flags.
* @param __HANDLE__: LTDC handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clears the LTDC pending flags.
* @param __HANDLE__: LTDC handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg LTDC_FLAG_LI: Line Interrupt flag
* @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag
* @arg LTDC_FLAG_TE: Transfer Error interrupt flag
* @arg LTDC_FLAG_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enables the specified LTDC interrupts.
* @param __HANDLE__: LTDC handle
* @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disables the specified LTDC interrupts.
* @param __HANDLE__: LTDC handle
* @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval None
*/
#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified LTDC interrupt has occurred or not.
* @param __HANDLE__: LTDC handle
* @param __INTERRUPT__: specifies the LTDC interrupt source to check.
* This parameter can be one of the following values:
* @arg LTDC_IT_LI: Line Interrupt flag
* @arg LTDC_IT_FU: FIFO Underrun Interrupt flag
* @arg LTDC_IT_TE: Transfer Error interrupt flag
* @arg LTDC_IT_RR: Register Reload Interrupt Flag
* @retval The state of INTERRUPT (SET or RESET).
*/
#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/**
* @}
*/
#if defined(DSI)
/* Include LTDC HAL Extension module */
#include "stm32h7xx_hal_ltdc_ex.h"
#endif /*DSI*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
* @{
*/
/** @addtogroup LTDC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
/**
* @}
*/
/** @addtogroup LTDC_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions *************************************************/
HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);
uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup LTDC_Private_Types LTDC Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup LTDC_Private_Variables LTDC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup LTDC_Private_Constants LTDC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup LTDC_Private_Macros LTDC Private Macros
* @{
*/
#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84 + (0x80*(__LAYER__)))))
#define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER)
#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))
#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))
#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH))
#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC))
#define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AVBP(__AVBP__) ((__AVBP__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_AAW(__AAW__) ((__AAW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_AAH(__AAH__) ((__AAH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_TOTALW(__TOTALW__) ((__TOTALW__) <= LTDC_HORIZONTALSYNC)
#define IS_LTDC_TOTALH(__TOTALH__) ((__TOTALH__) <= LTDC_VERTICALSYNC)
#define IS_LTDC_BLUEVALUE(__BBLUE__) ((__BBLUE__) <= LTDC_COLOR)
#define IS_LTDC_GREENVALUE(__BGREEN__) ((__BGREEN__) <= LTDC_COLOR)
#define IS_LTDC_REDVALUE(__BRED__) ((__BRED__) <= LTDC_COLOR)
#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \
((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))
#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR2__) (((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_CA) || \
((__BLENDING_FACTOR2__) == LTDC_BLENDING_FACTOR2_PAxCA))
#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \
((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))
#define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA)
#define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_VCONFIGST(__VCONFIGST__) ((__VCONFIGST__) <= LTDC_STARTPOSITION)
#define IS_LTDC_VCONFIGSP(__VCONFIGSP__) ((__VCONFIGSP__) <= LTDC_STOPPOSITION)
#define IS_LTDC_CFBP(__CFBP__) ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU)
#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LTDC_Private_Functions LTDC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_LTDC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h
+522
View File
@@ -0,0 +1,522 @@
/**
******************************************************************************
* @file stm32h7xx_hal_mdios.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of MDIOS HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_MDIOS_H
#define __STM32H7xx_HAL_MDIOS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup MDIOS
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Types MDIOS Exported Types
* @{
*/
/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
* @{
*/
typedef enum
{
HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_MDIOS_StateTypeDef;
/**
* @}
*/
/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
* @{
*/
typedef struct
{
uint32_t PortAddress; /*!< Specifies the MDIOS port address.
This parameter can be a value from 0 to 31 */
uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled.
This parameter can be a value of @ref MDIOS_Preamble_Check */
}MDIOS_InitTypeDef;
/**
* @}
*/
/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
* @{
*/
typedef struct
{
MDIOS_TypeDef *Instance; /*!< Register base address */
MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */
__IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */
HAL_LockTypeDef Lock; /*!< MDIOS Lock */
}MDIOS_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
* @{
*/
/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check
* @{
*/
#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
/**
* @}
*/
/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
* @{
*/
#define MDIOS_REG0 ((uint32_t)0x00000000U)
#define MDIOS_REG1 ((uint32_t)0x00000001U)
#define MDIOS_REG2 ((uint32_t)0x00000002U)
#define MDIOS_REG3 ((uint32_t)0x00000003U)
#define MDIOS_REG4 ((uint32_t)0x00000004U)
#define MDIOS_REG5 ((uint32_t)0x00000005U)
#define MDIOS_REG6 ((uint32_t)0x00000006U)
#define MDIOS_REG7 ((uint32_t)0x00000007U)
#define MDIOS_REG8 ((uint32_t)0x00000008U)
#define MDIOS_REG9 ((uint32_t)0x00000009U)
#define MDIOS_REG10 ((uint32_t)0x0000000AU)
#define MDIOS_REG11 ((uint32_t)0x0000000BU)
#define MDIOS_REG12 ((uint32_t)0x0000000CU)
#define MDIOS_REG13 ((uint32_t)0x0000000DU)
#define MDIOS_REG14 ((uint32_t)0x0000000EU)
#define MDIOS_REG15 ((uint32_t)0x0000000FU)
#define MDIOS_REG16 ((uint32_t)0x00000010U)
#define MDIOS_REG17 ((uint32_t)0x00000011U)
#define MDIOS_REG18 ((uint32_t)0x00000012U)
#define MDIOS_REG19 ((uint32_t)0x00000013U)
#define MDIOS_REG20 ((uint32_t)0x00000014U)
#define MDIOS_REG21 ((uint32_t)0x00000015U)
#define MDIOS_REG22 ((uint32_t)0x00000016U)
#define MDIOS_REG23 ((uint32_t)0x00000017U)
#define MDIOS_REG24 ((uint32_t)0x00000018U)
#define MDIOS_REG25 ((uint32_t)0x00000019U)
#define MDIOS_REG26 ((uint32_t)0x0000001AU)
#define MDIOS_REG27 ((uint32_t)0x0000001BU)
#define MDIOS_REG28 ((uint32_t)0x0000001CU)
#define MDIOS_REG29 ((uint32_t)0x0000001DU)
#define MDIOS_REG30 ((uint32_t)0x0000001EU)
#define MDIOS_REG31 ((uint32_t)0x0000001FU)
/**
* @}
*/
/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags
* @{
*/
#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)
/**
* @}
*/
/** @defgroup MDIOS_Interrupt_sources Interrupt Sources
* @{
*/
#define MDIOS_IT_WRITE MDIOS_CR_WRIE
#define MDIOS_IT_READ MDIOS_CR_RDIE
#define MDIOS_IT_ERROR MDIOS_CR_EIE
/**
* @}
*/
/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags
* @{
*/
#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF
/**
* @}
*/
/** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line
* @{
*/
#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x00000400) /* !< 42 - 32 = 10 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
* @{
*/
/** @brief Reset MDIOS handle state
* @param __HANDLE__: MDIOS handle.
* @retval None
*/
#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
/**
* @brief Enable/Disable the MDIOS peripheral.
* @param __HANDLE__: specifies the MDIOS handle.
* @retval None
*/
#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
/**
* @brief Enable the MDIOS device interrupt.
* @param __HANDLE__: specifies the MDIOS handle.
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
* @arg MDIOS_IT_ERROR: Error interrupt
* @retval None
*/
#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the MDIOS device interrupt.
* @param __HANDLE__: specifies the MDIOS handle.
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
* @arg MDIOS_IT_ERROR: Error interrupt
* @retval None
*/
#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/** @brief Set MDIOS slave get write register flag
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__: specifies the write register flag
* @retval The state of write flag
*/
#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
/** @brief MDIOS slave get read register flag
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__: specifies the read register flag
* @retval The state of read flag
*/
#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
/** @brief MDIOS slave get interrupt
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__ : specifies the Error flag.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
* @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
* @retval The state of the error flag
*/
#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
/** @brief MDIOS slave clear interrupt
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__ : specifies the Error flag.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
* @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
* @retval none
*/
#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
/**
* @brief Checks whether the specified MDIOS interrupt is set or not.
* @param __HANDLE__: specifies the MDIOS handle.
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
* @arg MDIOS_IT_ERROR: Error interrupt
* @retval The state of the interrupt source
*/
#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @brief Enable the MDIOS WAKEUP Exti Line.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.
* This parameter can be:
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR2 |= (__EXTI_LINE__))
/**
* @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval EXTI MDIOS WAKEUP Line Status.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 & (__EXTI_LINE__))
/**
* @brief Clear the MDIOS WAKEUP Exti flag.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.
* This parameter can be:
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR2 = (__EXTI_LINE__))
/**
* @brief enable rising edge interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
* This parameter can be:
* @arg ETH_WAKEUP_EXTI_LINE
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \
(EXTI->RTSR2 |= (__EXTI_LINE__))
/**
* @brief enable falling edge interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
* This parameter can be:
* @arg ETH_WAKEUP_EXTI_LINE
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\
(EXTI->FTSR2 |= (__EXTI_LINE__))
/**
* @brief enable falling edge interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
* This parameter can be:
* @arg ETH_WAKEUP_EXTI_LINE
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\
(EXTI->FTSR2 |= (__EXTI_LINE__))
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.
* This parameter can be:
* @arg MDIOS_WAKEUP_EXTI_LINE
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
* @{
*/
/** @addtogroup MDIOS_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
/**
* @}
*/
/** @addtogroup MDIOS_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data);
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData);
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
/**
* @}
*/
/** @addtogroup MDIOS_Exported_Functions_Group3
* @{
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);
HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup MDIOS_Private_Types MDIOS Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Variables MDIOS Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Constants MDIOS Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup MDIOS_Private_Macros MDIOS Private Macros
* @{
*/
#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_MDIOS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h
+852
View File
@@ -0,0 +1,852 @@
/**
******************************************************************************
* @file stm32h7xx_hal_mdma.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_MDMA_H
#define __STM32H7xx_HAL_MDMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup MDMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MDMA_Exported_Types MDMA Exported Types
* @brief MDMA Exported Types
* @{
*/
/**
* @brief MDMA Configuration Structure definition
*/
typedef struct
{
uint32_t Request; /*!< Specifies the MDMA request.
This parameter can be a value of @ref MDMA_Request_selection*/
uint32_t TransferTriggerMode; /*!< Specifies the Trigger Transfer mode : each request triggers a :
a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer
This parameter can be a value of @ref MDMA_Transfer_TriggerMode */
uint32_t Priority; /*!< Specifies the software priority for the MDMAy channelx.
This parameter can be a value of @ref MDMA_Priority_level */
uint32_t Endianness; /*!< Specifies if the MDMA transactions preserve the Little endianness.
This parameter can be a value of @ref MDMA_Endianness */
uint32_t SourceInc; /*!< Specifies if the Source increment mode .
This parameter can be a value of @ref MDMA_Source_increment_mode */
uint32_t DestinationInc; /*!< Specifies if the Destination increment mode .
This parameter can be a value of @ref MDMA_Destination_increment_mode */
uint32_t SourceDataSize; /*!< Specifies the source data size.
This parameter can be a value of @ref MDMA_Source_data_size */
uint32_t DestDataSize; /*!< Specifies the destination data size.
This parameter can be a value of @ref MDMA_Destination_data_size */
uint32_t DataAlignment; /*!< Specifies the source to destination Memory data packing/padding mode.
This parameter can be a value of @ref MDMA_data_Alignment */
uint32_t BufferTransferLength; /*!< Specifies the buffer Transfer Length (number of bytes),
this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/
uint32_t SourceBurst; /*!< Specifies the Burst transfer configuration for the source memory transfers.
It specifies the amount of data to be transferred in a single non interruptable
transaction.
This parameter can be a value of @ref MDMA_Source_burst
@note : the burst may be FIXED/INCR based on SourceInc value ,
the BURST must be programmed as to ensure that the burst size will be lower than than
BufferTransferLength */
uint32_t DestBurst; /*!< Specifies the Burst transfer configuration for the destination memory transfers.
It specifies the amount of data to be transferred in a single non interruptable
transaction.
This parameter can be a value of @ref MDMA_Destination_burst
@note : the burst may be FIXED/INCR based on DestinationInc value ,
the BURST must be programmed as to ensure that the burst size will be lower than than
BufferTransferLength */
int32_t SourceBlockAddressOffset; /*!< this field specifies the Next block source address offset
signed value : if > 0 then increment the next block source Address by offset from where the last block ends
if < 0 then decrement the next block source Address by offset from where the last block ends
if == 0, the next block source address starts from where the last block ends
*/
int32_t DestBlockAddressOffset; /*!< this field specifies the Next block destination address offset
signed value : if > 0 then increment the next block destination Address by offset from where the last block ends
if < 0 then decrement the next block destination Address by offset from where the last block ends
if == 0, the next block destination address starts from where the last block ends
*/
}MDMA_InitTypeDef;
/**
* @brief HAL MDMA linked list node structure definition
* @note The Linked list node allows to define a new MDMA configuration
* (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).
* When CLAR register is configured to a non NULL value , each time a transfer ends,
* a new configuration (linked list node) is automatically loaded from the address given in CLAR register.
*/
typedef struct
{
__IO uint32_t CTCR; /*!< New CTCR register configuration for the given MDMA linked list node */
__IO uint32_t CBNDTR; /*!< New CBNDTR register configuration for the given MDMA linked list node */
__IO uint32_t CSAR; /*!< New CSAR register configuration for the given MDMA linked list node */
__IO uint32_t CDAR; /*!< New CDAR register configuration for the given MDMA linked list node */
__IO uint32_t CBRUR; /*!< New CBRUR register configuration for the given MDMA linked list node */
__IO uint32_t CLAR; /*!< New CLAR register configuration for the given MDMA linked list node */
__IO uint32_t CTBR; /*!< New CTBR register configuration for the given MDMA linked list node */
__IO uint32_t Reserved; /*!< Reserved register*/
__IO uint32_t CMAR; /*!< New CMAR register configuration for the given MDMA linked list node */
__IO uint32_t CMDR; /*!< New CMDR register configuration for the given MDMA linked list node */
}MDMA_LinkNodeTypeDef;
/**
* @brief HAL MDMA linked list node configuration structure definition
* @note used with HAL_MDMA_LinkedList_CreateNode function
*/
typedef struct
{
MDMA_InitTypeDef Init; /*!< configuration of the specified MDMA Linked List Node */
uint32_t SrcAddress; /*!< The source memory address for the Linked list Node */
uint32_t DstAddress; /*!< The destination memory address for the Linked list Node */
uint32_t BlockDataLength; /*!< The length of a block transfer in bytes */
uint32_t BlockCount; /*!< The number of a blocks to be transfer */
uint32_t PostRequestMaskAddress; /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.
PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
uint32_t PostRequestMaskData; /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.
PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served */
}MDMA_LinkNodeConfTypeDef;
/**
* @brief HAL MDMA State structure definition
*/
typedef enum
{
HAL_MDMA_STATE_RESET = 0x00U, /*!< MDMA not yet initialized or disabled */
HAL_MDMA_STATE_READY = 0x01U, /*!< MDMA initialized and ready for use */
HAL_MDMA_STATE_BUSY = 0x02U, /*!< MDMA process is ongoing */
HAL_MDMA_STATE_ERROR = 0x03U, /*!< MDMA error state */
HAL_MDMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */
}HAL_MDMA_StateTypeDef;
/**
* @brief HAL MDMA Level Complete structure definition
*/
typedef enum
{
HAL_MDMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_MDMA_BUFFER_TRANSFER = 0x01U, /*!< Buffer Transfer */
HAL_MDMA_BLOCK_TRANSFER = 0x02U, /*!< Block Transfer */
HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U /*!< repeat block Transfer */
}HAL_MDMA_LevelCompleteTypeDef;
/**
* @brief HAL MDMA Callbacks IDs structure definition
*/
typedef enum
{
HAL_MDMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_MDMA_XFER_BUFFERCPLT_CB_ID = 0x01U, /*!< Buffer Transfer */
HAL_MDMA_XFER_BLOCKCPLT_CB_ID = 0x02U, /*!< Block Transfer */
HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID = 0x03U, /*!< Repeated Block Transfer */
HAL_MDMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
HAL_MDMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
HAL_MDMA_XFER_ALL_CB_ID = 0x06U /*!< All */
}HAL_MDMA_CallbackIDTypeDef;
/**
* @brief MDMA handle Structure definition
*/
typedef struct __MDMA_HandleTypeDef
{
MDMA_Channel_TypeDef *Instance; /*!< Register base address */
MDMA_InitTypeDef Init; /*!< MDMA communication parameters */
HAL_LockTypeDef Lock; /*!< MDMA locking object */
__IO HAL_MDMA_StateTypeDef State; /*!< MDMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer complete callback */
void (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA buffer transfer complete callback */
void (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer complete callback */
void (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback */
void (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer error callback */
void (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA transfer Abort callback */
MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress; /*!< specifies the first node address of the transfer list
(after the initial node defined by the Init struct)
this parameter is used internally by the MDMA driver
to construct the liked list node
*/
MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress; /*!< specifies the last node address of the transfer list
this parameter is used internally by the MDMA driver
to construct the liked list node
*/
uint32_t LinkedListNodeCounter; /*!< Number of nodes in the MDMA linked list */
__IO uint32_t ErrorCode; /*!< MDMA Error code */
} MDMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MDMA_Exported_Constants MDMA Exported Constants
* @brief MDMA Exported constants
* @{
*/
/** @defgroup MDMA_Error_Codes MDMA Error Codes
* @brief MDMA Error Codes
* @{
*/
#define HAL_MDMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_MDMA_ERROR_READ_XFER ((uint32_t)0x00000001U) /*!< Read Transfer error */
#define HAL_MDMA_ERROR_WRITE_XFER ((uint32_t)0x00000002U) /*!< Write Transfer error */
#define HAL_MDMA_ERROR_MASK_DATA ((uint32_t)0x00000004U) /*!< Error Mask Data error */
#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U) /*!< Linked list Data error */
#define HAL_MDMA_ERROR_ALIGNMENT ((uint32_t)0x00000010U) /*!< Address/Size alignment error */
#define HAL_MDMA_ERROR_BLOCK_SIZE ((uint32_t)0x00000020U) /*!< Block Size error */
#define HAL_MDMA_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
#define HAL_MDMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort or SW trigger requested with no Xfer ongoing */
#define HAL_MDMA_ERROR_BUSY ((uint32_t)0x00000100U) /*!< DeInit or SW trigger requested with Xfer ongoing */
/**
* @}
*/
/** @defgroup MDMA_Request_selection MDMA Request selection
* @brief MDMA_Request_selection
* @{
*/
#define MDMA_REQUEST_DMA1_Stream0_TC ((uint32_t)0x00000000U) /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag */
#define MDMA_REQUEST_DMA1_Stream1_TC ((uint32_t)0x00000001U) /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag */
#define MDMA_REQUEST_DMA1_Stream2_TC ((uint32_t)0x00000002U) /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag */
#define MDMA_REQUEST_DMA1_Stream3_TC ((uint32_t)0x00000003U) /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag */
#define MDMA_REQUEST_DMA1_Stream4_TC ((uint32_t)0x00000004U) /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag */
#define MDMA_REQUEST_DMA1_Stream5_TC ((uint32_t)0x00000005U) /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag */
#define MDMA_REQUEST_DMA1_Stream6_TC ((uint32_t)0x00000006U) /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag */
#define MDMA_REQUEST_DMA1_Stream7_TC ((uint32_t)0x00000007U) /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream0_TC ((uint32_t)0x00000008U) /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream1_TC ((uint32_t)0x00000009U) /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream2_TC ((uint32_t)0x0000000AU) /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream3_TC ((uint32_t)0x0000000BU) /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream4_TC ((uint32_t)0x0000000CU) /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream5_TC ((uint32_t)0x0000000DU) /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream6_TC ((uint32_t)0x0000000EU) /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag */
#define MDMA_REQUEST_DMA2_Stream7_TC ((uint32_t)0x0000000FU) /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag */
#define MDMA_REQUEST_LTDC_LINE_IT ((uint32_t)0x00000010U) /*!< MDMA HW request is LTDC Line interrupt Flag */
#define MDMA_REQUEST_JPEG_INFIFO_TH ((uint32_t)0x00000011U) /*!< MDMA HW request is JPEG Input FIFO threshold Flag */
#define MDMA_REQUEST_JPEG_INFIFO_NF ((uint32_t)0x00000012U) /*!< MDMA HW request is JPEG Input FIFO not full Flag */
#define MDMA_REQUEST_JPEG_OUTFIFO_TH ((uint32_t)0x00000013U) /*!< MDMA HW request is JPEG Output FIFO threshold Flag */
#define MDMA_REQUEST_JPEG_OUTFIFO_NE ((uint32_t)0x00000014U) /*!< MDMA HW request is JPEG Output FIFO not empty Flag */
#define MDMA_REQUEST_JPEG_END_CONVERSION ((uint32_t)0x00000015U) /*!< MDMA HW request is JPEG End of conversion Flag */
#define MDMA_REQUEST_QUADSPI_FIFO_TH ((uint32_t)0x00000016U) /*!< MDMA HW request is QSPI FIFO threshold Flag */
#define MDMA_REQUEST_QUADSPI_TC ((uint32_t)0x00000017U) /*!< MDMA HW request is QSPI Transfer complete Flag */
#define MDMA_REQUEST_DMA2D_CLUT_TC ((uint32_t)0x00000018U) /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag */
#define MDMA_REQUEST_DMA2D_TC ((uint32_t)0x00000019U) /*!< MDMA HW request is DMA2D Transfer Complete Flag */
#define MDMA_REQUEST_DMA2D_TW ((uint32_t)0x0000001AU) /*!< MDMA HW request is DMA2D Transfer Watermark Flag */
#if defined(DSI)
#define MDMA_REQUEST_DSI_TEARINGE_FFECT ((uint32_t)0x0000001BU) /*!< MDMA HW request is DSI Tearing Effect Flag */
#define MDMA_REQUEST_DSI_END_REFRESH ((uint32_t)0x0000001CU) /*!< MDMA HW request is DSI End of refresh Flag */
#endif /* DSI */
#define MDMA_REQUEST_SDMMC1_END_DATA ((uint32_t)0x0000001DU) /*!< MDMA HW request is SDMMC1 End of Data Flag */
#define MDMA_REQUEST_SW ((uint32_t)0x40000000U) /*!< MDMA SW request */
/**
* @}
*/
/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger Mode
* @brief MDMA Transfer Trigger Mode
* @{
*/
#define MDMA_BUFFER_TRANSFER ((uint32_t)0x00000000U) /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
#define MDMA_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_0) /*!< Each MDMA request (SW or HW) triggers a block transfer */
#define MDMA_REPEAT_BLOCK_TRANSFER ((uint32_t)MDMA_CTCR_TRGM_1) /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
#define MDMA_FULL_TRANSFER ((uint32_t)MDMA_CTCR_TRGM) /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
/**
* @}
*/
/** @defgroup MDMA_Priority_level MDMA Priority level
* @brief MDMA Priority level
* @{
*/
#define MDMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
#define MDMA_PRIORITY_MEDIUM ((uint32_t)MDMA_CCR_PL_0) /*!< Priority level: Medium */
#define MDMA_PRIORITY_HIGH ((uint32_t)MDMA_CCR_PL_1) /*!< Priority level: High */
#define MDMA_PRIORITY_VERY_HIGH ((uint32_t)MDMA_CCR_PL) /*!< Priority level: Very High */
/**
* @}
*/
/** @defgroup MDMA_Endianness MDMA Endianness
* @brief MDMA Endianness
* @{
*/
#define MDMA_LITTLE_ENDIANNESS_PRESERVE ((uint32_t)0x00000000U) /*!< little endianness preserve */
#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_BEX) /*!< BYTEs endianness exchange when destination data size is > Byte */
#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX) /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD*/
#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_WEX) /*!< WORDs endianness exchange when destination data size is > DOUBLE WORD */
/**
* @}
*/
/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode
* @brief MDMA Source increment mode
* @{
*/
#define MDMA_SRC_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
#define MDMA_SRC_INC_BYTE ((uint32_t)MDMA_CTCR_SINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
#define MDMA_SRC_INC_HALFWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
#define MDMA_SRC_INC_WORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
#define MDMA_SRC_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
#define MDMA_SRC_DEC_BYTE ((uint32_t)MDMA_CTCR_SINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
#define MDMA_SRC_DEC_HALFWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
#define MDMA_SRC_DEC_WORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
#define MDMA_SRC_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
/**
* @}
*/
/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode
* @brief MDMA Destination increment mode
* @{
*/
#define MDMA_DEST_INC_DISABLE ((uint32_t)0x00000000U) /*!< Source address pointer is fixed */
#define MDMA_DEST_INC_BYTE ((uint32_t)MDMA_CTCR_DINC_1) /*!< Source address pointer is incremented by a BYTE (8 bits)*/
#define MDMA_DEST_INC_HALFWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
#define MDMA_DEST_INC_WORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
#define MDMA_DEST_INC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is incremented by a double Word (64 bits)) */
#define MDMA_DEST_DEC_BYTE ((uint32_t)MDMA_CTCR_DINC) /*!< Source address pointer is decremented by a BYTE (8 bits)*/
#define MDMA_DEST_DEC_HALFWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is decremented by a half Word (16 bits) */
#define MDMA_DEST_DEC_WORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is decremented by a Word (32 bits)*/
#define MDMA_DEST_DEC_DOUBLEWORD ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS) /*!< Source address pointer is decremented by a double Word (64 bits)) */
/**
* @}
*/
/** @defgroup MDMA_Source_data_size MDMA Source data size
* @brief MDMA Source data size
* @{
*/
#define MDMA_SRC_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Source data size is Byte */
#define MDMA_SRC_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_SSIZE_0) /*!< Source data size is half word */
#define MDMA_SRC_DATASIZE_WORD ((uint32_t)MDMA_CTCR_SSIZE_1) /*!< Source data size is word */
#define MDMA_SRC_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_SSIZE) /*!< Source data size is double word */
/**
* @}
*/
/** @defgroup MDMA_Destination_data_size MDMA Destination data size
* @brief MDMA Destination data size
* @{
*/
#define MDMA_DEST_DATASIZE_BYTE ((uint32_t)0x00000000U) /*!< Destination data size is Byte */
#define MDMA_DEST_DATASIZE_HALFWORD ((uint32_t)MDMA_CTCR_DSIZE_0) /*!< Destination data size is half word */
#define MDMA_DEST_DATASIZE_WORD ((uint32_t)MDMA_CTCR_DSIZE_1) /*!< Destination data size is word */
#define MDMA_DEST_DATASIZE_DOUBLEWORD ((uint32_t)MDMA_CTCR_DSIZE) /*!< Destination data size is double word */
/**
* @}
*/
/** @defgroup MDMA_data_Alignment MDMA data alignment
* @brief MDMA MDMA data alignment
* @{
*/
#define MDMA_DATAALIGN_PACKENABLE ((uint32_t)MDMA_CTCR_PKE) /*!< The source data is packed/un-packed into the destination data size
All data are right aligned, in Little Endien mode. */
#define MDMA_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< Right Aligned, padded w/ 0s (default) */
#define MDMA_DATAALIGN_RIGHT_SIGNED ((uint32_t)MDMA_CTCR_PAM_0) /*!< Right Aligned, Sign extended ,
Note : this mode is allowed only if the Source data size smaller than Destination data size */
#define MDMA_DATAALIGN_LEFT ((uint32_t)MDMA_CTCR_PAM_1) /*!< Left Aligned (padded with 0s) */
/**
* @}
*/
/** @defgroup MDMA_Source_burst MDMA Source burst
* @brief MDMA Source burst
* @{
*/
#define MDMA_SOURCE_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
#define MDMA_SOURCE_BURST_2BEATS ((uint32_t)MDMA_CTCR_SBURST_0) /*!< Burst 2 beats */
#define MDMA_SOURCE_BURST_4BEATS ((uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 4 beats */
#define MDMA_SOURCE_BURST_8BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
#define MDMA_SOURCE_BURST_16BEATS ((uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 16 beats */
#define MDMA_SOURCE_BURST_32BEATS ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
#define MDMA_SOURCE_BURST_64BEATS ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
#define MDMA_SOURCE_BURST_128BEATS ((uint32_t)MDMA_CTCR_SBURST) /*!< Burst 128 beats */
/**
* @}
*/
/** @defgroup MDMA_Destination_burst MDMA Destination burst
* @brief MDMA Destination burst
* @{
*/
#define MDMA_DEST_BURST_SINGLE ((uint32_t)0x00000000U) /*!< single transfer */
#define MDMA_DEST_BURST_2BEATS ((uint32_t)MDMA_CTCR_DBURST_0) /*!< Burst 2 beats */
#define MDMA_DEST_BURST_4BEATS ((uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 4 beats */
#define MDMA_DEST_BURST_8BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1) /*!< Burst 8 beats */
#define MDMA_DEST_BURST_16BEATS ((uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 16 beats */
#define MDMA_DEST_BURST_32BEATS ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 32 beats */
#define MDMA_DEST_BURST_64BEATS ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2) /*!< Burst 64 beats */
#define MDMA_DEST_BURST_128BEATS ((uint32_t)MDMA_CTCR_DBURST) /*!< Burst 128 beats */
/**
* @}
*/
/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions
* @brief MDMA interrupt enable definitions
* @{
*/
#define MDMA_IT_TE ((uint32_t)MDMA_CCR_TEIE) /*!< Transfer Error interrupt */
#define MDMA_IT_CTC ((uint32_t)MDMA_CCR_CTCIE) /*!< Channel Transfer Complete interrupt */
#define MDMA_IT_BRT ((uint32_t)MDMA_CCR_BRTIE) /*!< Block Repeat Transfer interrupt */
#define MDMA_IT_BT ((uint32_t)MDMA_CCR_BTIE) /*!< Block Transfer interrupt */
#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE) /*!< Buffer Transfer Complete interrupt */
/**
* @}
*/
/** @defgroup MDMA_flag_definitions MDMA flag definitions
* @brief MDMA flag definitions
* @{
*/
#define MDMA_FLAG_TE ((uint32_t)MDMA_CISR_TEIF) /*!< Transfer Error flag */
#define MDMA_FLAG_CTC ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
#define MDMA_FLAG_BRT ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
#define MDMA_FLAG_BT ((uint32_t)MDMA_CISR_BTIF) /*!< Block Transfer complete flag */
#define MDMA_FLAG_BFTC ((uint32_t)MDMA_CISR_TCIF) /*!< BuFfer Transfer complete flag */
#define MDMA_FLAG_CRQA ((uint32_t)MDMA_CISR_CRQA) /*!< Channel ReQest Active flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup MDMA_Exported_Macros MDMA Exported Macros
* @{
*/
/**
* @brief Enable the specified MDMA Channel.
* @param __HANDLE__: MDMA handle
* @retval None
*/
#define __HAL_MDMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= MDMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__: MDMA handle
* @retval None
*/
#define __HAL_MDMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~MDMA_CCR_EN)
/**
* @brief Get the MDMA Channel pending flags.
* @param __HANDLE__: MDMA handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
* @arg MDMA_FLAG_TE : Transfer Error flag.
* @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
* @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
* @arg MDMA_FLAG_BT : Block Transfer complete flag.
* @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
* @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CISR & (__FLAG__))
/**
* @brief Clear the MDMA Stream pending flags.
* @param __HANDLE__: MDMA handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg MDMA_FLAG_TE : Transfer Error flag.
* @arg MDMA_FLAG_CTC : Channel Transfer Complete flag.
* @arg MDMA_FLAG_BRT : Block Repeat Transfer flag.
* @arg MDMA_FLAG_BT : Block Transfer complete flag.
* @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.
* @retval None
*/
#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))
/**
* @brief Enables the specified DMA Channel interrupts.
* @param __HANDLE__: MDMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
* @arg MDMA_IT_BT : Block Transfer interrupt mask
* @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
* @retval None
*/
#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disables the specified MDMA Channel interrupts.
* @param __HANDLE__: MDMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
* @arg MDMA_IT_BT : Block Transfer interrupt mask
* @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
* @retval None
*/
#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified MDMA Channel interrupt is enabled or not.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt source to check.
* @arg MDMA_IT_TE : Transfer Error interrupt mask
* @arg MDMA_IT_CTC : Channel Transfer Complete interrupt mask
* @arg MDMA_IT_BRT : Block Repeat Transfer interrupt mask
* @arg MDMA_IT_BT : Block Transfer interrupt mask
* @arg MDMA_IT_BFTC : BuFfer Transfer Complete interrupt mask
* @retval The state of MDMA_IT (SET or RESET).
*/
#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDMA_Exported_Functions MDMA Exported Functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);
HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);
HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);
HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));
HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/* Linked list operation functions ********************************************/
/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions
* @brief Linked list operation functions
* @{
*/
HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);
HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);
HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);
HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);
HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions
* @brief I/O operation functions
* @{
*/
HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);
HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);
HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);
HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, uint32_t CompleteLevel, uint32_t Timeout);
HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);
void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
* @{
*/
HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);
uint32_t HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup MDMA_Private_Types MDMA Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup MDMA_Private_Defines MDMA Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup MDMA_Private_Variables MDMA Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup MDMA_Private_Constants MDMA Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup MDMA_Private_Macros MDMA Private Macros
* @{
*/
#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER ) || \
((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \
((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \
((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW ) || \
((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
((__PRIORITY__) == MDMA_PRIORITY_HIGH) || \
((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE ) || \
((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE) || \
((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))
#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE ) || \
((__INC__) == MDMA_SRC_INC_BYTE ) || \
((__INC__) == MDMA_SRC_INC_HALFWORD ) || \
((__INC__) == MDMA_SRC_INC_WORD ) || \
((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \
((__INC__) == MDMA_SRC_DEC_BYTE) || \
((__INC__) == MDMA_SRC_DEC_HALFWORD) || \
((__INC__) == MDMA_SRC_DEC_WORD) || \
((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))
#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE ) || \
((__INC__) == MDMA_DEST_INC_BYTE ) || \
((__INC__) == MDMA_DEST_INC_HALFWORD ) || \
((__INC__) == MDMA_DEST_INC_WORD ) || \
((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \
((__INC__) == MDMA_DEST_DEC_BYTE) || \
((__INC__) == MDMA_DEST_DEC_HALFWORD) || \
((__INC__) == MDMA_DEST_DEC_WORD) || \
((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))
#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE ) || \
((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \
((__SIZE__) == MDMA_SRC_DATASIZE_WORD ) || \
((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))
#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE ) || \
((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \
((__SIZE__) == MDMA_DEST_DATASIZE_WORD ) || \
((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED ) || \
((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \
((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \
((__BURST__) == MDMA_SOURCE_BURST_8BEATS) || \
((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \
((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \
((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \
((__BURST__) == MDMA_SOURCE_BURST_128BEATS))
#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \
((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \
((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \
((__BURST__) == MDMA_DEST_BURST_8BEATS) || \
((__BURST__) == MDMA_DEST_BURST_16BEATS) || \
((__BURST__) == MDMA_DEST_BURST_32BEATS) || \
((__BURST__) == MDMA_DEST_BURST_64BEATS) || \
((__BURST__) == MDMA_DEST_BURST_128BEATS))
#define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER ) || \
((__MODE__) == MDMA_BLOCK_TRANSFER ) || \
((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
((__MODE__) == MDMA_FULL_TRANSFER))
#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001) && ((__LENGTH__) < 0x000000FF))
#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0 ) && ((__COUNT__) <= 4096))
#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0) && ((SIZE) <= 65536))
#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MDMA_Private_Functions MDMA Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_MDMA_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h
+707
View File
@@ -0,0 +1,707 @@
/**
******************************************************************************
* @file stm32h7xx_hal_mmc.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of MMC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_MMC_H
#define __STM32H7xx_HAL_MMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_sdmmc.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup MMC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MMC_Exported_Types MMC Exported Types
* @{
*/
/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
* @{
*/
typedef enum
{
HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
}HAL_MMC_StateTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
* @{
*/
typedef enum
{
HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
}HAL_MMC_CardStateTypedef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
* @{
*/
#define MMC_InitTypeDef SDMMC_InitTypeDef
#define MMC_TypeDef SDMMC_TypeDef
/**
* @brief MMC Card Information Structure definition
*/
typedef struct
{
uint32_t CardType; /*!< Specifies the card Type */
uint32_t Class; /*!< Specifies the class of the card class */
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
uint32_t BlockSize; /*!< Specifies one block size in bytes */
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
}HAL_MMC_CardInfoTypeDef;
/**
* @brief MMC handle Structure definition
*/
typedef struct
{
MMC_TypeDef *Instance; /*!< MMC registers base address */
MMC_InitTypeDef Init; /*!< MMC required parameters */
HAL_LockTypeDef Lock; /*!< MMC locking object */
uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
uint32_t TxXferSize; /*!< MMC Tx Transfer size */
uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
uint32_t RxXferSize; /*!< MMC Rx Transfer size */
__IO uint32_t Context; /*!< MMC transfer context */
__IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
__IO uint32_t ErrorCode; /*!< MMC Card Error codes */
HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
uint32_t CSD[4]; /*!< MMC card specific data table */
uint32_t CID[4]; /*!< MMC card identification number table */
}MMC_HandleTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
* @{
*/
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
__IO uint8_t SysSpecVersion; /*!< System specification version */
__IO uint8_t Reserved1; /*!< Reserved */
__IO uint8_t TAAC; /*!< Data read access time 1 */
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
__IO uint16_t CardComdClasses; /*!< Card command classes */
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
__IO uint8_t DSRImpl; /*!< DSR implemented */
__IO uint8_t Reserved2; /*!< Reserved */
__IO uint32_t DeviceSize; /*!< Device Size */
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
__IO uint8_t EraseGrSize; /*!< Erase group size */
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGrouop; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
__IO uint8_t FileFormat; /*!< File format */
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_MMC_CardCSDTypeDef;
/**
* @}
*/
/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
* @{
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
__IO uint32_t ProdName1; /*!< Product Name part1 */
__IO uint8_t ProdName2; /*!< Product Name part2 */
__IO uint8_t ProdRev; /*!< Product Revision */
__IO uint32_t ProdSN; /*!< Product Serial Number */
__IO uint8_t Reserved1; /*!< Reserved1 */
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_MMC_CardCIDTypedef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MMC_Exported_Constants Exported Constants
* @{
*/
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
* @{
*/
#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
* @{
*/
#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
* @{
*/
/**
* @brief
*/
#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
/**
* @}
*/
/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
* @{
*/
#define MMC_LOW_CAPACITY_CARD ((uint32_t)0x00000000U) /*!< MMC Card Capacity <=2Gbytes */
#define MMC_HIGH_CAPACITY_CARD ((uint32_t)0x00000001U) /*!< MMC Card Capacity >2Gbytes and <2Tbytes */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup MMC_Exported_macros MMC Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the MMC device interrupt.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the MMC device interrupt.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified MMC flag is set or not.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
* @retval The new state of MMC FLAG (SET or RESET).
*/
#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the MMC's pending flags.
* @param __HANDLE__: MMC Handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
* @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
* @retval None
*/
#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified MMC interrupt has occurred or not.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
* @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval The new state of MMC IT (SET or RESET).
*/
#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the MMC's interrupt pending bits.
* @param __HANDLE__: MMC Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @}
*/
/* Include MMC HAL Extension module */
#include "stm32h7xx_hal_mmc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMC_Exported_Functions MMC Exported Functions
* @{
*/
/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
/* Callback in non blocking modes (DMA) */
void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
* @{
*/
HAL_MMC_CardStateTypedef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypedef *pCID);
HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup MMC_Private_Types MMC Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup MMC_Private_Defines MMC Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup MMC_Private_Variables MMC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup MMC_Private_Constants MMC Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup MMC_Private_Macros MMC Private Macros
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MMC_Private_Functions MMC Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_MMC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_mmc_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of MMC HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_MMC_EX_H
#define __STM32H7xx_HAL_MMC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup MMCEx
* @brief MMC HAL extended module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Types MMCEx Exported Types
* @{
*/
/** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure
* @{
*/
typedef enum
{
MMC_DMA_BUFFER0 = 0x00U, /*!< selects MMC internal DMA Buffer 0 */
MMC_DMA_BUFFER1 = 0x01U, /*!< selects MMC internal DMA Buffer 1 */
}HAL_MMCEx_DMABuffer_MemoryTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions
* @{
*/
/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_MMCEx_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h
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/**
******************************************************************************
* @file stm32h7xx_hal_nand.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_NAND_H
#define __STM32H7xx_HAL_NAND_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_fmc.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup NAND
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Types NAND Exported Types
* @{
*/
/**
* @brief HAL NAND State structures definition
*/
typedef enum
{
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
}HAL_NAND_StateTypeDef;
/**
* @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
/*<! NAND memory electronic signature maker and device IDs */
uint8_t Maker_Id;
uint8_t Device_Id;
uint8_t Third_Id;
uint8_t Fourth_Id;
}NAND_IDTypeDef;
/**
* @brief NAND Memory address Structure definition
*/
typedef struct
{
uint16_t Page; /*!< NAND memory Page address */
uint16_t Plane; /*!< NAND memory Zone address */
uint16_t Block; /*!< NAND memory Block address */
}NAND_AddressTypeDef;
/**
* @brief NAND Memory info Structure definition
*/
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
for 8 bits adressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
uint32_t PlaneNbr; /*!< NAND memory number of planes */
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
}NAND_DeviceConfigTypeDef;
/**
* @brief NAND handle Structure definition
*/
typedef struct
{
FMC_NAND_TypeDef *Instance; /*!< Register base address */
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NAND locking object */
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
}NAND_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
/** @brief Reset NAND handle state
* @param __HANDLE__: specifies the NAND handle.
* @retval None
*/
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* NAND Control functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE ((uint32_t)0x80000000U)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define NAND_CMD_READID ((uint8_t)0x90U)
#define NAND_CMD_STATUS ((uint8_t)0x70U)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define NAND_CMD_RESET ((uint8_t)0xFFU)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define NAND_BUSY ((uint32_t)0x00000000U)
#define NAND_ERROR ((uint32_t)0x00000001U)
#define NAND_READY ((uint32_t)0x00000040U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NAND_Private_Macros NAND Private Macros
* @{
*/
/**
* @brief NAND memory address computation.
* @param __ADDRESS__: NAND memory address.
* @param __HANDLE__ : NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
* @brief NAND memory address cycling.
* @param __ADDRESS__: NAND memory address.
* @retval NAND address cycling value.
*/
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
/**
* @brief NAND memory Columns cycling.
* @param __ADDRESS__: NAND memory address.
* @retval NAND Column address cycling value.
*/
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_NAND_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h
+299
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@@ -0,0 +1,299 @@
/**
******************************************************************************
* @file stm32h7xx_hal_nor.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_NOR_H
#define __STM32H7xx_HAL_NOR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_fmc.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup NOR
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup NOR_Exported_Types NOR Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
}HAL_NOR_StateTypeDef;
/**
* @brief FMC NOR Status typedef
*/
typedef enum
{
HAL_NOR_STATUS_SUCCESS = 0U,
HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT
}HAL_NOR_StatusTypeDef;
/**
* @brief FMC NOR ID typedef
*/
typedef struct
{
uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory. */
uint16_t Device_Code1;
uint16_t Device_Code2;
uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
These codes can be accessed by performing read operations with specific
control signals and addresses set.They can also be accessed by issuing
an Auto Select command. */
}NOR_IDTypeDef;
/**
* @brief FMC NOR CFI typedef
*/
typedef struct
{
/*!< Defines the information stored in the memory's Common flash interface
which contains a description of various electrical and timing parameters,
density information and functions supported by the memory */
uint16_t CFI_1;
uint16_t CFI_2;
uint16_t CFI_3;
uint16_t CFI_4;
}NOR_CFITypeDef;
/**
* @brief NOR handle Structure definition
*/
typedef struct
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NOR locking object */
__IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
}NOR_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NOR_Exported_Macros NOR Exported Macros
* @{
*/
/** @brief Reset NOR handle state
* @param __HANDLE__: specifies the NOR handle.
* @retval None
*/
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup NOR_Exported_Functions NOR Exported Functions
* @{
*/
/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
* @{
*/
/* NOR Control functions *****************************************************/
HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
/**
* @}
*/
/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
* @{
*/
/* NOR State functions ********************************************************/
HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NOR_Private_Constants NOR Private Constants
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000U)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x61U)
#define CFI2_ADDRESS ((uint16_t)0x62U)
#define CFI3_ADDRESS ((uint16_t)0x63U)
#define CFI4_ADDRESS ((uint16_t)0x64U)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x0U)
#define NOR_MEMORY_16B ((uint8_t)0x1U)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NOR_Private_Macros NOR Private Macros
* @{
*/
/**
* @brief NOR memory address shifting.
* @param __NOR_ADDRESS: NOR base address
* @param __NOR_MEMORY_WIDTH_: NOR memory width
* @param __ADDRESS__: NOR memory address
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
/**
* @brief NOR memory write data to specified address.
* @param __ADDRESS__: NOR memory address
* @param __DATA__: Data to write
* @retval None
*/
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
(*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
__DSB(); \
} while(0)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_NOR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h
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/**
******************************************************************************
* @file stm32h7xx_hal_opamp.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_OPAMP_H
#define __STM32H7xx_HAL_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup OPAMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
* @{
*/
/**
* @brief OPAMP Init structure definition
*/
typedef struct
{
uint32_t PowerMode; /*!< Specifies the power mode Normal or High Speed.
This parameter must be a value of @ref OPAMP_PowerMode */
uint32_t Mode; /*!< Specifies the OPAMP mode
This parameter must be a value of @ref OPAMP_Mode
mode is either Standalone, - Follower or PGA */
uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & PGA modes
- In Standalone mode i.e when mode is OPAMP_STANDALONE_MODE
This parameter must be a value of @ref OPAMP_InvertingInput
- In Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
& In PGA mode i.e when mode is OPAMP_PGA_MODE
This parameter is Not Applicable */
uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
This parameter must be a value of @ref OPAMP_NonInvertingInput */
uint32_t PgaGain; /*!< Specifies the gain in PGA mode
i.e. when mode is OPAMP_PGA_MODE.
This parameter must be a value of @ref OPAMP_PgaGain */
uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
i.e. when mode is OPAMP_PGA_MODE
This parameter must be a value of @ref OPAMP_PgaConnect
Either: not connected, connected to VINM0, connected to VINM1
(VINM0 or VINM1 are typically used for external filtering) */
uint32_t UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref OPAMP_UserTrimming
UserTrimming is either factory or user trimming.*/
uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS) in Normal Mode
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 0 and Max_Data = 31.
16 is typical default value */
uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS) in Normal Mode
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 0 and Max_Data = 31.
16 is typical default value */
uint32_t TrimmingValuePHighSpeed; /*!< Specifies the offset trimming value (PMOS) in High Speed Mode
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 0 and Max_Data = 31.
16 is typical default value */
uint32_t TrimmingValueNHighSpeed; /*!< Specifies the offset trimming value (NMOS) in High Speed Mode
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 0 and Max_Data = 31.
16 is typical default value */
}OPAMP_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_OPAMP_STATE_RESET = 0x00000000, /*!< OPAMP is not yet Initialized */
HAL_OPAMP_STATE_READY = 0x00000001, /*!< OPAMP is initialized and ready for use */
HAL_OPAMP_STATE_CALIBBUSY = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
HAL_OPAMP_STATE_BUSY = 0x00000004, /*!< OPAMP is enabled and running in normal mode */
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005 /*!< OPAMP is locked
only system reset allows reconfiguring the opamp. */
}HAL_OPAMP_StateTypeDef;
/**
* @brief OPAMP Handle Structure definition
*/
typedef struct
{
OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
} OPAMP_HandleTypeDef;
/**
* @brief HAl_OPAMP_TrimmingValueTypeDef definition
*/
typedef uint32_t HAL_OPAMP_TrimmingValueTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
* @{
*/
/** @defgroup OPAMP_Mode OPAMP Mode
* @{
*/
#define OPAMP_STANDALONE_MODE ((uint32_t)0x00000000) /*!< standalone mode */
#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
#define OPAMP_FOLLOWER_MODE (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0) /*!< follower mode */
/**
* @}
*/
/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
* @{
*/
#define OPAMP_NONINVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP non-inverting input connected to dedicated IO pin */
#define OPAMP_NONINVERTINGINPUT_DAC_CH OPAMP_CSR_VPSEL_0 /*!< OPAMP non-inverting input connected internally to DAC channel */
/**
* @}
*/
/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
* @{
*/
#define OPAMP_INVERTINGINPUT_IO0 ((uint32_t)0x00000000) /*!< OPAMP inverting input connected to dedicated IO pin */
#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to dedicated IO pin */
/**
* @}
*/
/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
* @{
*/
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO ((uint32_t)0x00000000) /*!< In PGA mode, the inverting input is not connected */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_2 /*!< In PGA mode, the inverting input is connected to VINM0 */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the inverting input is connected to VINM0 or bias */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the inverting input is connected to VINM0 or bias , VINM1 connected for filtering */
/**
* @}
*/
/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
* @{
*/
#define OPAMP_PGA_GAIN_2_OR_MINUS_1 ((uint32_t)0x00000000) /*!< PGA gain could be 2 or -1 */
#define OPAMP_PGA_GAIN_4_OR_MINUS_3 OPAMP_CSR_PGGAIN_0 /*!< PGA gain could be 4 or -3 */
#define OPAMP_PGA_GAIN_8_OR_MINUS_7 OPAMP_CSR_PGGAIN_1 /*!< PGA gain could be 8 or -7 */
#define OPAMP_PGA_GAIN_16_OR_MINUS_15 (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1) /*!< PGA gain could be 16 or -15 */
/**
* @}
*/
/** @defgroup OPAMP_PowerMode OPAMP PowerMode
* @{
*/
#define OPAMP_POWERMODE_NORMAL ((uint32_t)0x00000000)
#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_OPAHSM
/**
* @}
*/
/** @defgroup OPAMP_VREF OPAMP VREF
* @{
*/
#define OPAMP_VREF_3VDDA ((uint32_t)0x00000000) /*!< OPAMP Vref = 3.3% VDDA */
#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPAMP Vref = 10% VDDA */
#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPAMP Vref = 50% VDDA */
#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPAMP Vref = 90% VDDA */
/**
* @}
*/
/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
* @{
*/
#define OPAMP_TRIMMING_FACTORY ((uint32_t)0x00000000) /*!< Factory trimming */
#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
/**
* @}
*/
/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
* @{
*/
#define OPAMP_FACTORYTRIMMING_DUMMY ((uint32_t)0xFFFFFFFF) /*!< Dummy value if trimming value could not be retrieved */
#define OPAMP_FACTORYTRIMMING_N ((uint32_t)0x00000000) /*!< Offset trimming N */
#define OPAMP_FACTORYTRIMMING_P ((uint32_t)0x00000001) /*!< Offset trimming P */
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
* @brief OPAMP Private constants and defines
* @{
*/
/* NONINVERTING bit position in OTR & HSOTR */
#define OPAMP_INPUT_NONINVERTING ((uint32_t) 8) /*!< Non inverting input */
/* Offset trimming time: during calibration, minimum time needed between two */
/* steps to have 1 mV accuracy. */
/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=2ms.*/
/* Unit: ms. */
#define OPAMP_TRIMMING_DELAY ((uint32_t) 2)
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
* @{
*/
/** @brief Reset OPAMP handle state.
* @param __HANDLE__: OPAMP handle.
* @retval None
*/
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup OPAMP_Private_Macros OPAMP Private Macros
* @{
*/
#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
((INPUT) == OPAMP_PGA_MODE) || \
((INPUT) == OPAMP_FOLLOWER_MODE))
#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_INVERTINGINPUT_IO1))
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))
#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15))
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
((VREF) == OPAMP_VREF_10VDDA) || \
((VREF) == OPAMP_VREF_50VDDA) || \
((VREF) == OPAMP_VREF_90VDDA))
#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
((TRIMMING) == OPAMP_POWERMODE_HIGHSPEED) )
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
((TRIMMING) == OPAMP_TRIMMING_USER))
#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
/**
* @}
*/
/* Include OPAMP HAL Extended module */
#include "stm32h7xx_hal_opamp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OPAMP_Exported_Functions
* @{
*/
/** @addtogroup OPAMP_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @addtogroup OPAMP_Exported_Functions_Group2
* @{
*/
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @addtogroup OPAMP_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
/**
* @}
*/
/** @addtogroup OPAMP_Exported_Functions_Group4
* @{
*/
/* Peripheral State functions **************************************************/
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_OPAMP_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp_ex.h
+101
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/**
******************************************************************************
* @file stm32h7xx_hal_opamp_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of OPAMP HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_OPAMP_EX_H
#define __STM32H7xx_HAL_OPAMP_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup OPAMPEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
* @{
*/
/* Extended IO operation functions *****************************************************/
/** @addtogroup OPAMPEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup OPAMPEx_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_OPAMP_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd.h
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/**
******************************************************************************
* @file stm32h7xx_hal_pcd.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_PCD_H
#define __STM32H7xx_HAL_PCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_usb.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup PCD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PCD_Exported_Types PCD Exported Types
* @{
*/
/**
* @brief PCD State structure definition
*/
typedef enum
{
HAL_PCD_STATE_RESET = 0x00U,
HAL_PCD_STATE_READY = 0x01U,
HAL_PCD_STATE_ERROR = 0x02U,
HAL_PCD_STATE_BUSY = 0x03U,
HAL_PCD_STATE_TIMEOUT = 0x04U
} PCD_StateTypeDef;
/* Device LPM suspend state */
typedef enum
{
LPM_L0 = 0x00U, /* on */
LPM_L1 = 0x01U, /* LPM L1 sleep */
LPM_L2 = 0x02U, /* suspend */
LPM_L3 = 0x03U, /* off */
}PCD_LPM_StateTypeDef;
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
/**
* @brief PCD Handle Structure definition
*/
typedef struct
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
This parameter can be set to ENABLE or DISABLE */
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
This parameter can be set to ENABLE or DISABLE */
void *pData; /*!< Pointer to upper stack Handler */
} PCD_HandleTypeDef;
/**
* @}
*/
/* Include PCD HAL Extension module */
#include "stm32h7xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0U
#define PCD_SPEED_HIGH_IN_FULL 1U
#define PCD_SPEED_FULL 2U
/**
* @}
*/
/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1U
#define PCD_PHY_EMBEDDED 2U
/**
* @}
*/
/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5U
#endif /* USBD_HS_TRDT_VALUE */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_ENABLE(__HANDLE__) USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
~(USB_OTG_PCGCCTL_STOPCLK)
#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM43) /*!< External interrupt line 43 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)EXTI_IMR2_IM44) /*!< External interrupt line 44 Connected to the USB FS EXTI Line */
/* HS */
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
EXTI->FTSR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
EXTI->RTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
EXTI->FTSR2 |= USB_OTG_HS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_HS_WAKEUP_EXTI_LINE)
/* FS */
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI_D1->IMR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI_D1->PR2 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI_D1->PR2 = USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->FTSR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
EXTI->RTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
EXTI->FTSR2 |= USB_OTG_FS_WAKEUP_EXTI_LINE
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER2 |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
/** @defgroup PCD_Instance_definition PCD Instance definition
* @{
*/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB1_OTG_HS) || \
((INSTANCE) == USB2_OTG_FS))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_PCD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pcd_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_PCD_EX_H
#define __STM32H7xx_HAL_PCD_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup PCDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00U, /* on */
PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */
}PCD_LPM_MsgTypeDef;
typedef enum
{
PCD_BCD_ERROR = 0xFF,
PCD_BCD_CONTACT_DETECTION = 0xFE,
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
}PCD_BCD_MsgTypeDef;
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_PCD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h
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/**
******************************************************************************
* @file stm32h7xx_hal_pwr.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_PWR_H
#define __STM32H7xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode */
}PWR_PVDTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_PVD_detection_level PWR PVD detection level
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0
#define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1
#define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2
#define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3
#define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4
#define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5
#define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6
#define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7/* External input analog voltage (Compare internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
/**
* @}
*/
/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
#define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1)
#define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0)
/**
* @}
*/
/** @defgroup PWR_Flag PWR Flag
* @{
*/
#define PWR_FLAG_STOP ((uint8_t)0x01U)
#define PWR_FLAG_SB_D1 ((uint8_t)0x02U)
#define PWR_FLAG_SB_D2 ((uint8_t)0x03U)
#define PWR_FLAG_SB ((uint8_t)0x04U)
#define PWR_FLAG_PVDO ((uint8_t)0x07U)
#define PWR_FLAG_AVDO ((uint8_t)0x08U)
#define PWR_FLAG_ACTVOSRDY ((uint8_t)0x09U)
#define PWR_FLAG_ACTVOS ((uint8_t)0x0AU)
#define PWR_FLAG_BRR ((uint8_t)0x0BU)
#define PWR_FLAG_VOSRDY ((uint8_t)0x0CU)
#if defined(SMPS)
#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x0DU)
#else
#define PWR_FLAG_SCUEN ((uint8_t)0x0DU)
#endif /* SMPS */
/**
* @}
*/
/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
* @{
*/
#define PWR_EWUP_MASK ((uint32_t)0x0FFF3F3FU)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Macro PWR Exported Macro
* @{
*/
/** @brief macros configure the main internal regulator output voltage.
* @param __REGULATOR__: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do { \
__IO uint32_t tmpreg = 0x00; \
MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
UNUSED(tmpreg); \
} while(0)
/** @brief Check PWR PVD/AVD and VOSflags are set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
* by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset
* until the PVDE bit is set.
* @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
* by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode
* For this reason, this bit is equal to 0 after Standby or reset
* until the AVDE bit is set.
* @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
* scaling output selection is ready.
* @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
* when the device wakes up from Standby mode or by a system reset
* or power reset.
* @arg PWR_FLAG_SB: StandBy flag
* @arg PWR_FLAG_STOP: STOP flag
* @arg PWR_FLAG_SB_D1: StandBy D1 flag
* @arg PWR_FLAG_SB_D2: StandBy D2 flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
/** @brief Clear the PWR's flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg PWR_FLAG_SB: StandBy flag.
* @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
* @retval None.
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
/**
* @brief Enable the PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable event on PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable event on PVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief PVD EXTI line configuration: set rising & falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Check whether the specified PVD EXTI interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
/**
* @brief Clear the PVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_PVD)
/**
* @brief Generates a Software interrupt on PVD EXTI line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Include PWR HAL Extension module */
#include "stm32h7xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions **********************************************/
/* PVD configuration */
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration */
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes entry */
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
/* Power PVD IRQ Handler */
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
/* Cortex System Control functions *******************************************/
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PWR_Private_Constants PWR Private Constants
* @{
*/
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
* @{
*/
/*!< External interrupt line 16 Connected to the PVD EXTI Line */
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR1_IM16)
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros
* @{
*/
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_PVD_MODE_NORMAL))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_PWR_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h
+614
View File
@@ -0,0 +1,614 @@
/**
******************************************************************************
* @file stm32h7xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_PWR_EX_H
#define __STM32H7xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWREx Exported Types
* @{
*/
/**
* @brief PWREx AVD configuration structure definition
*/
typedef struct
{
uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level.
This parameter can be a value of @ref PWREx_AVD_detection_level */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWREx_AVD_Mode */
}PWREx_AVDTypeDef;
/**
* @brief PWREx Wakeup pin configuration structure definition
*/
typedef struct
{
uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
This parameter can be a value of @ref PWREx_WakeUp_Pins */
uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
This parameter can be a value of @ref PWREx_PIN_Polarity */
uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull.
This parameter can be a value of @ref PWREx_PIN_Pull */
}PWREx_WakeupPinTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
* @{
*/
/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
* @{
*/
#define PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN_6
#define PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN_5
#define PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN_4
#define PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN_3
#define PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN_2
#define PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN_1
/* High level and No pull */
#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN_6
#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN_5
#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN_4
#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN_3
#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN_2
#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN_1
/* Low level and No pull */
#define PWR_WAKEUP_PIN6_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_6 | PWR_WKUPEPR_WKUPEN_6)
#define PWR_WAKEUP_PIN5_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_5 | PWR_WKUPEPR_WKUPEN_5)
#define PWR_WAKEUP_PIN4_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_4 | PWR_WKUPEPR_WKUPEN_4)
#define PWR_WAKEUP_PIN3_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_3 | PWR_WKUPEPR_WKUPEN_3)
#define PWR_WAKEUP_PIN2_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_2 | PWR_WKUPEPR_WKUPEN_2)
#define PWR_WAKEUP_PIN1_LOW (uint32_t)(PWR_WKUPEPR_WKUPP_1 | PWR_WKUPEPR_WKUPEN_1)
/* Wake-Up Pins EXTI register mask */
#define PWR_EXTI_WAKEUP_PINS_MASK (uint32_t)(EXTI_IMR2_IM55 | EXTI_IMR2_IM56 | \
EXTI_IMR2_IM57 | EXTI_IMR2_IM58 | \
EXTI_IMR2_IM59 | EXTI_IMR2_IM60)
/* Wake-Up Pins EXTI register offset */
#define PWR_EXTI_WAKEUP_PINS_PULL_POSITION_OFFSET 23U
/* Wake-Up Pins PWR register offsets */
#define PWR_WAKEUP_PINS_POLARITY_REGISTER_OFFSET 8U
#define PWR_WAKEUP_PINS_PULL_REGISTER_OFFSET 16U
#define PWR_WAKEUP_PINS_PULL_POSITION_OFFSET 2U
/**
* @}
*/
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
* @{
*/
#define PWR_PIN_POLARITY_HIGH ((uint32_t)0x00000000U)
#define PWR_PIN_POLARITY_LOW ((uint32_t)0x00000001U)
/**
* @}
*/
/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
* @{
*/
#define PWR_PIN_NO_PULL ((uint32_t)0x00000000U)
#define PWR_PIN_PULL_UP ((uint32_t)0x00000001U)
#define PWR_PIN_PULL_DOWN ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
* @{
*/
#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */
#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */
#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */
#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */
#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */
#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */
/**
* @}
*/
/** @defgroup PWREx_Domains PWREx Domains definition
* @{
*/
#define PWR_D1_DOMAIN ((uint32_t)0x00000000U)
#define PWR_D2_DOMAIN ((uint32_t)0x00000001U)
#define PWR_D3_DOMAIN ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
* @{
*/
#define PWR_CPU_FLAGS ((uint32_t)0x00000000U)
/**
* @}
*/
/** @defgroup PWREx_D3_State PWREx D3 Domain State
* @{
*/
#define PWR_D3_DOMAIN_STOP ((uint32_t)0x00000000U)
#define PWR_D3_DOMAIN_RUN ((uint32_t)0x00000800U)
/**
* @}
*/
/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
* @{
*/
#define PWR_LDO_SUPPLY PWR_CR3_LDOEN /* Core domains are suppplied from the LDO */
#if defined(SMPS)
#define PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /* Core domains are suppplied from the SMPS only */
#define PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 1.8V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 2.5V output supplies the LDO which supplies the Core domains */
#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /* The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
#define PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /* The SMPS 1.8V output supplies an external source which supplies the Core domains */
#define PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /* The SMPS 2.5V output supplies an external source which supplies the Core domains */
#endif /* SMPS */
#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /* The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source */
#if defined(SMPS)
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#else
#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
#endif /* SMPS */
/**
* @}
*/
#if defined(SMPS)
/** @defgroup HAL_PWREx_SMPS_SetOperationMode PWREx SMPS operation modes
* @{
*/
#define PWR_SMPS_FORCED_PWM PWR_PDR1_SMPSFPWMEN
#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL0 PWR_PDR1_PSKSYNC
#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL1 (PWR_PDR1_PSKSYNC | PWR_PDR1_PSKTHR_0)
#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL2 (PWR_PDR1_PSKSYNC | PWR_PDR1_PSKTHR_1)
#define PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL3 (PWR_PDR1_PSKSYNC | PWR_PDR1_PSKTHR)
#define PWR_SMPS_FAST_PULSE_SKIPPING (PWR_PDR1_FASTTRAN |PWR_PDR1_PSKSYNC)
#define PWR_SMPS_ULTRA_FAST_PULSE_SKIPPING PWR_PDR1_FASTTRAN
#define PWR_SMPS_MODE_MASK (PWR_PDR1_FASTTRAN | PWR_PDR1_PSKTHR | PWR_PDR1_PSKSYNC | PWR_PDR1_SMPSFPWMEN)
/**
* @}
*/
#endif /* SMPS */
/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
* @{
*/
#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0
#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1
#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2
#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3
/**
* @}
*/
/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
* @{
*/
#define PWR_AVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Basic mode is used */
#define PWR_AVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
#define PWR_REGULATOR_SVOS_SCALE3 (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_CR3_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
* @{
*/
#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define PWR_VBAT_BELOW_LOW_THRESHOLD PWR_CR2_VBATL
#define PWR_VBAT_ABOVE_HIGH_THRESHOLD PWR_CR2_VBATH
/**
* @}
*/
/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
* @{
*/
#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD ((uint32_t)0x00000000U)
#define PWR_TEMP_BELOW_LOW_THRESHOLD PWR_CR2_TEMPL
#define PWR_TEMP_ABOVE_HIGH_THRESHOLD PWR_CR2_TEMPH
/**
* @}
*/
/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
* @{
*/
#define PWR_EXTI_LINE_AVD ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macro PWREx Exported Macro
* @{
*/
/**
* @brief Enable the AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD EXTI Line 16
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI_D1->IMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI_D1->EMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief AVD EXTI line configuration: set rising & falling edge trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Check whether the specified AVD EXTI interrupt flag is set or not.
* @retval EXTI AVD Line Status.
*/
#define __HAL_PWR_AVD_EXTI_GET_FLAG() READ_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
/**
* @brief Clear the AVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI_D1->PR1, PWR_EXTI_LINE_AVD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions
* @{
*/
/* Power supply control functions */
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
uint32_t HAL_PWREx_GetSupplyConfig(void);
#if defined(SMPS)
uint32_t HAL_PWREx_SMPS_SetOperationMode(uint32_t SMPS_Mode);
#endif /*SMPS*/
/* Power volatge scaling functions */
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions
* @{
*/
/* System low power control functions */
void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
/* Flash low power control functions */
void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
/* Wakeup Pins control functions */
void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
/* Power Wakeup PIN IRQ Handler */
void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
void HAL_PWREx_WKUP1_Callback(void);
void HAL_PWREx_WKUP2_Callback(void);
void HAL_PWREx_WKUP3_Callback(void);
void HAL_PWREx_WKUP4_Callback(void);
void HAL_PWREx_WKUP5_Callback(void);
void HAL_PWREx_WKUP6_Callback(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions
* @{
*/
/* Backup regulator control functions */
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
/* USB regulator control functions */
HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
void HAL_PWREx_EnableUSBVoltageDetector(void);
void HAL_PWREx_DisableUSBVoltageDetector(void);
/* Battery control functions */
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
void HAL_PWREx_DisableBatteryCharging(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions
* @{
*/
/* Power VBAT/Temperature monitoring functions */
void HAL_PWREx_EnableMonitoring(void);
void HAL_PWREx_DisableMonitoring(void);
uint32_t HAL_PWREx_GetTemperatureLevel(void);
uint32_t HAL_PWREx_GetVBATLevel(void);
/* Power AVD configuration functions */
void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
void HAL_PWREx_EnableAVD(void);
void HAL_PWREx_DisableAVD(void);
/* Power PVD/AVD IRQ Handler */
void HAL_PWREx_PVD_AVD_IRQHandler(void);
void HAL_PWREx_AVDCallback(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PWREx_Private_Macros PWREx Private Macros
* @{
*/
/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
* @{
*/
#if defined(SMPS)
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT) || \
((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT) || \
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
#define IS_PWR_SMPS_MODE(MODE) (((MODE) == PWR_SMPS_FORCED_PWM) || \
((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL0) || \
((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL1) || \
((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL2) || \
((MODE) == PWR_SMPS_SLOW_PULSE_SKIPPING_LEVEL3) || \
((MODE) == PWR_SMPS_FAST_PULSE_SKIPPING) || \
((MODE) == PWR_SMPS_ULTRA_FAST_PULSE_SKIPPING))
#else
#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
#endif /*SMPS*/
#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) || \
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) || \
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) || \
((DOMAIN) == PWR_D2_DOMAIN) || \
((DOMAIN) == PWR_D3_DOMAIN))
#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
((PIN) == PWR_WAKEUP_PIN2) || \
((PIN) == PWR_WAKEUP_PIN3) || \
((PIN) == PWR_WAKEUP_PIN4) || \
((PIN) == PWR_WAKEUP_PIN5) || \
((PIN) == PWR_WAKEUP_PIN6) || \
((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
((PIN) == PWR_WAKEUP_PIN6_HIGH) || \
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
((PIN) == PWR_WAKEUP_PIN2_LOW) || \
((PIN) == PWR_WAKEUP_PIN3_LOW) || \
((PIN) == PWR_WAKEUP_PIN4_LOW) || \
((PIN) == PWR_WAKEUP_PIN5_LOW) || \
((PIN) == PWR_WAKEUP_PIN6_LOW))
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
((POLARITY) == PWR_PIN_POLARITY_LOW))
#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) || \
((PULL) == PWR_PIN_PULL_UP) || \
((PULL) == PWR_PIN_PULL_DOWN))
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) || \
((FLAG) == PWR_WAKEUP_FLAG2) || \
((FLAG) == PWR_WAKEUP_FLAG3) || \
((FLAG) == PWR_WAKEUP_FLAG4) || \
((FLAG) == PWR_WAKEUP_FLAG5) || \
((FLAG) == PWR_WAKEUP_FLAG6))
#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))
#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \
((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \
((MODE) == PWR_AVD_MODE_NORMAL))
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_PWR_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h
+694
View File
@@ -0,0 +1,694 @@
/**
******************************************************************************
* @file stm32h7xx_hal_qspi.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_QSPI_H
#define __STM32H7xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_mdma.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup QSPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup QSPI_Exported_Types QSPI Exported Types
* @{
*/
/**
* @brief QSPI Init structure definition
*/
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 32 */
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
/**
* @brief HAL QSPI State structures definition
*/
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
}HAL_QSPI_StateTypeDef;
/**
* @brief QSPI Handle Structure definition
*/
typedef struct
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
uint32_t Timeout; /* Timeout for the QSPI memory access */
}QSPI_HandleTypeDef;
/**
* @brief QSPI Command structure definition
*/
typedef struct
{
uint32_t Instruction; /* Specifies the Instruction to be sent
This parameter can be a value (8-bit) between 0x00 and 0xFF */
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AddressSize; /* Specifies the Address Size
This parameter can be a value of @ref QSPI_AddressSize */
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
This parameter can be a value of @ref QSPI_AlternateBytesSize */
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
This parameter can be a number between 0 and 31 */
uint32_t InstructionMode; /* Specifies the Instruction Mode
This parameter can be a value of @ref QSPI_InstructionMode */
uint32_t AddressMode; /* Specifies the Address Mode
This parameter can be a value of @ref QSPI_AddressMode */
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
uint32_t NbData; /* Specifies the number of data to transfer.
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
system clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
/**
* @brief QSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
This parameter can be any value between 0 and 0xFFFF */
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
This parameter can be any value between 1 and 4 */
uint32_t MatchMode; /* Specifies the method used for determining a match.
This parameter can be a value of @ref QSPI_MatchMode */
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
This parameter can be a value of @ref QSPI_AutomaticStop */
}QSPI_AutoPollingTypeDef;
/**
* @brief QSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
/**
* @}
*/
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
*/
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
/**
* @}
*/
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
*/
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
*/
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/
/**
* @}
*/
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
/**
* @}
*/
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
/**
* @}
*/
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
/**
* @}
*/
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
/**
* @}
*/
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
/**
* @}
*/
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
#define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
/**
* @}
*/
/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
*/
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
/**
* @}
*/
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
*/
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
*/
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
*/
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
*/
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
*/
/** @defgroup QSPI_Flags QSPI Flags
* @{
*/
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
/**
* @}
*/
/** @defgroup QSPI_Interrupts QSPI Interrupts
* @{
*/
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
/**
* @}
*/
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
* @brief QSPI Timeout definition
* @{
*/
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
* @{
*/
/** @brief Reset QSPI handle state.
* @param __HANDLE__: QSPI handle.
* @retval None
*/
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
/** @brief Enable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
* @param __HANDLE__: specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval None
*/
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Disable the specified QSPI interrupt.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval None
*/
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __INTERRUPT__: specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Check whether the selected QSPI flag is set or not.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
/** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__: specifies the QSPI Handle.
* @param __FLAG__: specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup QSPI_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
/* QSPI indirect mode */
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
/* QSPI status flag polling mode */
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
/* QSPI indirect mode */
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI status flag polling mode */
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI memory-mapped mode */
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32))
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \
((FLASH) == QSPI_FLASH_ID_2))
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
((MODE) == QSPI_DUALFLASH_DISABLE))
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
((MODE) == QSPI_INSTRUCTION_4_LINES))
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
((MODE) == QSPI_ADDRESS_1_LINE) || \
((MODE) == QSPI_ADDRESS_2_LINES) || \
((MODE) == QSPI_ADDRESS_4_LINES))
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
((MODE) == QSPI_DATA_1_LINE) || \
((MODE) == QSPI_DATA_2_LINES) || \
((MODE) == QSPI_DATA_4_LINES))
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
((MODE) == QSPI_MATCH_MODE_OR))
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_QSPI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_rng.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_RNG_H
#define __STM32H7xx_HAL_RNG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup RNG RNG
* @brief RNG HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RNG_Exported_Types RNG Exported Types
* @{
*/
/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
* @{
*/
typedef struct
{
uint32_t ClockErrorDetection; /*!< CED Clock error detection */
}RNG_InitTypeDef;
/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
* @{
*/
typedef enum
{
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
}HAL_RNG_StateTypeDef;
/**
* @}
*/
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
* @{
*/
typedef struct
{
RNG_TypeDef *Instance; /*!< Register base address */
RNG_InitTypeDef Init; /*!< RNG parameters */
HAL_LockTypeDef Lock; /*!< RNG locking object */
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
uint32_t RandomNumber; /*!< Last Generated RNG Data */
}RNG_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RNG_Exported_Constants RNG Exported Constants
* @{
*/
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
* @{
*/
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
/**
* @}
*/
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
* @{
*/
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
/**
* @}
*/
/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
* @{
*/
#define RNG_CED_ENABLE ((uint32_t)0x00000000) /*!< Clock error detection Enabled*/
#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RNG_Exported_Macros RNG Exported Macros
* @{
*/
/** @brief Reset RNG handle state
* @param __HANDLE__: RNG Handle
* @retval None
*/
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
/**
* @brief Enables the RNG peripheral.
* @param __HANDLE__: RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
/**
* @brief Disables the RNG peripheral.
* @param __HANDLE__: RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
/**
* @brief Check the selected RNG flag status.
* @param __HANDLE__: RNG Handle
* @param __FLAG__: RNG flag
* This parameter can be one of the following values:
* @arg RNG_FLAG_DRDY: Data ready
* @arg RNG_FLAG_CECS: Clock error current status
* @arg RNG_FLAG_SECS: Seed error current status
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clears the selected RNG flag status.
* @param __HANDLE__: RNG handle
* @param __FLAG__: RNG flag to clear
* @note WARNING: This is a dummy macro for HAL code alignment,
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
* @retval None
*/
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
/**
* @brief Enables the RNG interrupts.
* @param __HANDLE__: RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
/**
* @brief Disables the RNG interrupts.
* @param __HANDLE__: RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
* @param __HANDLE__: RNG Handle
* @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
* This parameter can be one of the following values:
* @arg RNG_IT_DRDY: Data ready interrupt
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clear the RNG interrupt status flags.
* @param __HANDLE__: RNG Handle
* @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
* This parameter can be one of the following values:
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
* @retval None
*/
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RNG_Exported_Functions RNG Exported Functions
* @{
*/
/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
/**
* @}
*/
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
/**
* @}
*/
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup RNG_Private_Types RNG Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup RNG_Private_Defines RNG Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup RNG_Private_Variables RNG Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RNG_Private_Constants RNG Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RNG_Private_Macros RNG Private Macros
* @{
*/
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
((IT) == RNG_IT_SEI))
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
((FLAG) == RNG_FLAG_CECS) || \
((FLAG) == RNG_FLAG_SECS))
#define IS_RNG_CED(CED) (((CED) == RNG_CED_ENABLE) || \
((CED) == RNG_CED_DISABLE))
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup RNG_Private_Functions RNG Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_RNG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h
+862
View File
@@ -0,0 +1,862 @@
/**
******************************************************************************
* @file stm32h7xx_hal_rtc.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_RTC_H
#define __STM32H7xx_HAL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
}HAL_RTCStateTypeDef;
/**
* @brief RTC Configuration Structure definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
}RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit
in CR register to store the operation.
This parameter can be a value of @ref RTC_StoreOperation_Definitions */
}RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
}RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
uint32_t Alarm; /*!< Specifies the alarm .
This parameter can be a value of @ref RTC_Alarms_Definitions */
}RTC_AlarmTypeDef;
/**
* @brief Time Handle Structure definition
*/
typedef struct
{
RTC_TypeDef *Instance; /*!< Register base address */
RTC_InitTypeDef Init; /*!< RTC required parameters */
HAL_LockTypeDef Lock; /*!< RTC locking object */
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
}RTC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
/**
* @}
*/
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
/**
* @}
*/
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE)
/**
* @}
*/
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
* @{
*/
#define RTC_OUTPUT_REMAP_NONE ((uint32_t)0x00000000)
#define RTC_OUTPUT_REMAP_POS1 ((uint32_t)RTC_OR_OUT_RMP)
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
/**
* @}
*/
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
#define RTC_FORMAT_BIN ((uint32_t)0x00000000)
#define RTC_FORMAT_BCD ((uint32_t)0x00000001)
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
/**
* @}
*/
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
/**
* @}
*/
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
/**
* @}
*/
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
/**
* @}
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
comparison. Only SS[0] is compared. */
#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
comparison. Only SS[1:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
comparison. Only SS[2:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
comparison. Only SS[3:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
comparison. Only SS[4:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
comparison. Only SS[5:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
comparison. Only SS[6:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
comparison. Only SS[7:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
comparison. Only SS[8:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
comparison. Only SS[9:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
comparison. Only SS[10:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
comparison.Only SS[11:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
comparison. Only SS[12:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
to activate alarm. */
/**
* @}
*/
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) /*!< Enable Timestamp Interrupt */
#define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) /*!< Enable Wakeup timer Interrupt */
#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) /*!< Enable Alarm A Interrupt */
#define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) /*!< Enable Alarm B Interrupt */
#define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /*!< Enable all Tamper Interrupt */
#define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt */
#define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt */
#define RTC_IT_TAMP3 ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt */
/**
* @}
*/
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* @{
*/
#define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF)
#define RTC_FLAG_TAMP3F ((uint32_t)RTC_ISR_TAMP3F)
#define RTC_FLAG_TAMP2F ((uint32_t)RTC_ISR_TAMP2F)
#define RTC_FLAG_TAMP1F ((uint32_t)RTC_ISR_TAMP1F)
#define RTC_FLAG_TSOVF ((uint32_t)RTC_ISR_TSOVF)
#define RTC_FLAG_TSF ((uint32_t)RTC_ISR_TSF)
#define RTC_FLAG_ITSF ((uint32_t)RTC_ISR_ITSF)
#define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF)
#define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF)
#define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF)
#define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF)
#define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF)
#define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS)
#define RTC_FLAG_SHPF ((uint32_t)RTC_ISR_SHPF)
#define RTC_FLAG_WUTWF ((uint32_t)RTC_ISR_WUTWF)
#define RTC_FLAG_ALRBWF ((uint32_t)RTC_ISR_ALRBWF)
#define RTC_FLAG_ALRAWF ((uint32_t)RTC_ISR_ALRAWF)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
/** @brief Reset RTC handle state
* @param __HANDLE__: RTC handle.
* @retval None
*/
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
/**
* @brief Disable the write protection for RTC registers.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xCA; \
(__HANDLE__)->Instance->WPR = 0x53; \
} while(0)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFF; \
} while(0)
/**
* @brief Enable the RTC ALARMA peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
/**
* @brief Disable the RTC ALARMA peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
/**
* @brief Enable the RTC ALARMB peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
/**
* @brief Disable the RTC ALARMB peripheral.
* @param __HANDLE__: specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
/**
* @brief Enable the RTC Alarm interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
/**
* @brief Get the selected RTC Alarm's flag status.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Alarm Flag sources to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
* @arg RTC_FLAG_ALRAWF
* @arg RTC_FLAG_ALRBWF
* @retval None
*/
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
/**
* @brief Clear the RTC Alarm's pending flags.
* @param __HANDLE__: specifies the RTC handle.
* @param __FLAG__: specifies the RTC Alarm Flag sources to clear.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
* @retval None
*/
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
/**
* @brief Check whether the specified RTC Alarm interrupt is enabled or not.
* @param __HANDLE__: specifies the RTC handle.
* @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
/**
* @brief Enable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable event on the RTC Alarm associated Exti line.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Clear the RTC Alarm associated Exti line flag.
* @retval None.
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Generate a Software interrupt on RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @}
*/
/* Include RTC HAL Extended module */
#include "stm32h7xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RTC_Exported_Functions
* @{
*/
/** @addtogroup RTC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group2
* @{
*/
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group3
* @{
*/
/* RTC Alarm functions ********************************************************/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group4
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
/**
* @}
*/
/** @addtogroup RTC_Exported_Functions_Group5
* @{
*/
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define RTC_TIMEOUT_VALUE 1000
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
* @{
*/
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
((REMAP) == RTC_OUTPUT_REMAP_POS1))
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F)
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF)
#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59)
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup RTC_Private_Functions
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_RTC_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32h7xx_hal_sai.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SAI_H
#define __STM32H7xx_HAL_SAI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SAI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SAI_Exported_Types SAI Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
} HAL_SAI_StateTypeDef;
/**
* @brief SAI Callback prototype
*/
typedef void (*SAIcallback)(void);
/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
* @brief SAI PDM Init structure definition
* @{
*/
typedef struct
{
FunctionalState Activation; /*!< Enable/Disable PDM interface */
uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used.
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
} SAI_PdmInitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
* @brief SAI Init Structure definition
* @{
*/
typedef struct
{
uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
This parameter can be a value of @ref SAI_Block_Mode */
uint32_t Synchro; /*!< Specifies SAI Block synchronization
This parameter can be a value of @ref SAI_Block_Synchronization */
uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
for BlockA and BlockB
This parameter can be a value of @ref SAI_Block_SyncExt
@note: If both audio blocks of same SAI are used, this parameter has
to be set to the same value for each audio block */
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
This parameter can be a value of @ref SAI_Block_Output_Drive
@note this value has to be set before enabling the audio block
but after the audio block configuration. */
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
This parameter can be a value of @ref SAI_Block_NoDivider
@note: If bit NOMCK in the SAI_xCR1 register is cleared, the frame length
should be aligned to a number equal to a power of 2, from 8 to 256.
If bit NOMCK in the SAI_xCR1 register is set, the frame length can
take any of the values without constraint since the input clock of
the audio block should be equal to the bit clock.
There is no MCLK_x clock which can be output. */
uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
uint32_t Mckdiv; /*!< Specifies the master clock divider, the parameter will be used if for
AudioFrequency the user choice
This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
uint32_t CompandingMode; /*!< Specifies the companding mode type.
This parameter can be a value of @ref SAI_Block_Companding_Mode */
uint32_t TriState; /*!< Specifies the companding mode type.
This parameter can be a value of @ref SAI_TRIState_Management */
SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */
/* This part of the structure is automatically filled if your are using the high level initialisation
function HAL_SAI_InitProtocol */
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
This parameter can be a value of @ref SAI_Block_Protocol */
uint32_t DataSize; /*!< Specifies the SAI Block data size.
This parameter can be a value of @ref SAI_Block_Data_Size */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
} SAI_InitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
* @brief SAI Frame Init structure definition
* @{
*/
typedef struct
{
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
This parameter must be a number between Min_Data = 8 and Max_Data = 256.
@note: If master clock MCLK_x pin is declared as an output, the frame length
should be aligned to a number equal to power of 2 in order to keep
in an audio frame, an integer number of MCLK pulses by bit Clock. */
uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
This Parameter specifies the length in number of bit clock (SCK + 1)
of the active level of FS signal in audio frame.
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
This parameter can be a value of @ref SAI_Block_FS_Definition */
uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
This parameter can be a value of @ref SAI_Block_FS_Polarity */
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
This parameter can be a value of @ref SAI_Block_FS_Offset */
} SAI_FrameInitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
* @brief SAI Block Slot Init Structure definition
* @{
*/
typedef struct
{
uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
uint32_t SlotSize; /*!< Specifies the Slot Size.
This parameter can be a value of @ref SAI_Block_Slot_Size */
uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
This parameter can be a value of @ref SAI_Block_Slot_Active */
} SAI_SlotInitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
* @brief SAI handle Structure definition
* @{
*/
typedef struct __SAI_HandleTypeDef
{
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
SAI_InitTypeDef Init; /*!< SAI communication parameters */
SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
uint16_t XferSize; /*!< SAI transfer size */
uint16_t XferCount; /*!< SAI transfer counter */
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
SAIcallback mutecallback; /*!< SAI mute callback */
void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
HAL_LockTypeDef Lock; /*!< SAI locking object */
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
__IO uint32_t ErrorCode; /*!< SAI Error code */
} SAI_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SAI_Exported_Constants SAI Exported Constants
* @{
*/
/** @defgroup SAI_Error_Code SAI Error Code
* @{
*/
#define HAL_SAI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_SAI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun Error */
#define HAL_SAI_ERROR_UDR ((uint32_t)0x00000002U) /*!< Underrun error */
#define HAL_SAI_ERROR_AFSDET ((uint32_t)0x00000004U) /*!< Anticipated Frame synchronisation detection */
#define HAL_SAI_ERROR_LFSDET ((uint32_t)0x00000008U) /*!< Late Frame synchronisation detection */
#define HAL_SAI_ERROR_CNREADY ((uint32_t)0x00000010U) /*!< codec not ready */
#define HAL_SAI_ERROR_WCKCFG ((uint32_t)0x00000020U) /*!< Wrong clock configuration */
#define HAL_SAI_ERROR_TIMEOUT ((uint32_t)0x00000040U) /*!< Timeout error */
#define HAL_SAI_ERROR_DMA ((uint32_t)0x00000080U) /*!< DMA error */
/**
* @}
*/
/** @defgroup SAI_Block_SyncExt SAI External synchronisation
* @{
*/
#define SAI_SYNCEXT_DISABLE 0
#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1
#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2
/**
* @}
*/
/** @defgroup SAI_Protocol SAI Supported protocol
* @{
*/
#define SAI_I2S_STANDARD 0
#define SAI_I2S_MSBJUSTIFIED 1
#define SAI_I2S_LSBJUSTIFIED 2
#define SAI_PCM_LONG 3
#define SAI_PCM_SHORT 4
/**
* @}
*/
/** @defgroup SAI_Protocol_DataSize SAI protocol data size
* @{
*/
#define SAI_PROTOCOL_DATASIZE_16BIT 0
#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1
#define SAI_PROTOCOL_DATASIZE_24BIT 2
#define SAI_PROTOCOL_DATASIZE_32BIT 3
/**
* @}
*/
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
* @{
*/
#define SAI_AUDIO_FREQUENCY_192K ((uint32_t)192000U)
#define SAI_AUDIO_FREQUENCY_96K ((uint32_t)96000U)
#define SAI_AUDIO_FREQUENCY_48K ((uint32_t)48000U)
#define SAI_AUDIO_FREQUENCY_44K ((uint32_t)44100U)
#define SAI_AUDIO_FREQUENCY_32K ((uint32_t)32000U)
#define SAI_AUDIO_FREQUENCY_22K ((uint32_t)22050U)
#define SAI_AUDIO_FREQUENCY_16K ((uint32_t)16000U)
#define SAI_AUDIO_FREQUENCY_11K ((uint32_t)11025U)
#define SAI_AUDIO_FREQUENCY_8K ((uint32_t)8000U)
#define SAI_AUDIO_FREQUENCY_MCKDIV ((uint32_t)0U)
/**
* @}
*/
/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
* @{
*/
#define SAI_MCK_OVERSAMPLING_DISABLE ((uint32_t)0x00000000U)
#define SAI_MCK_OVERSAMPLING_ENABLE ((uint32_t)SAI_xCR1_OSR)
/**
* @}
*/
/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
* @{
*/
#define SAI_PDM_CLOCK1_ENABLE ((uint32_t)SAI_PDMCR_CKEN1)
#define SAI_PDM_CLOCK2_ENABLE ((uint32_t)SAI_PDMCR_CKEN2)
#define SAI_PDM_CLOCK3_ENABLE ((uint32_t)SAI_PDMCR_CKEN3)
#define SAI_PDM_CLOCK4_ENABLE ((uint32_t)SAI_PDMCR_CKEN4)
/**
* @}
*/
/** @defgroup SAI_Block_Mode SAI Block Mode
* @{
*/
#define SAI_MODEMASTER_TX ((uint32_t)0x00000000U)
#define SAI_MODEMASTER_RX ((uint32_t)SAI_xCR1_MODE_0)
#define SAI_MODESLAVE_TX ((uint32_t)SAI_xCR1_MODE_1)
#define SAI_MODESLAVE_RX ((uint32_t)(SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0))
/**
* @}
*/
/** @defgroup SAI_Block_Protocol SAI Block Protocol
* @{
*/
#define SAI_FREE_PROTOCOL ((uint32_t)0x00000000U)
#define SAI_SPDIF_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_0)
#define SAI_AC97_PROTOCOL ((uint32_t)SAI_xCR1_PRTCFG_1)
/**
* @}
*/
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
* @{
*/
#define SAI_DATASIZE_8 ((uint32_t)SAI_xCR1_DS_1)
#define SAI_DATASIZE_10 ((uint32_t)(SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
#define SAI_DATASIZE_16 ((uint32_t)SAI_xCR1_DS_2)
#define SAI_DATASIZE_20 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_0))
#define SAI_DATASIZE_24 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1))
#define SAI_DATASIZE_32 ((uint32_t)(SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0))
/**
* @}
*/
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
* @{
*/
#define SAI_FIRSTBIT_MSB ((uint32_t)0x00000000U)
#define SAI_FIRSTBIT_LSB ((uint32_t)SAI_xCR1_LSBFIRST)
/**
* @}
*/
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
* @{
*/
#define SAI_CLOCKSTROBING_FALLINGEDGE 0
#define SAI_CLOCKSTROBING_RISINGEDGE 1
/**
* @}
*/
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
* @{
*/
#define SAI_ASYNCHRONOUS 0 /*!< Asynchronous */
#define SAI_SYNCHRONOUS 1 /*!< Synchronous with other block of same SAI */
#define SAI_SYNCHRONOUS_EXT_SAI1 2 /*!< Synchronous with other SAI, SAI1 */
#define SAI_SYNCHRONOUS_EXT_SAI2 3 /*!< Synchronous with other SAI, SAI2 */
/**
* @}
*/
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
* @{
*/
#define SAI_OUTPUTDRIVE_DISABLE ((uint32_t)0x00000000U)
#define SAI_OUTPUTDRIVE_ENABLE ((uint32_t)SAI_xCR1_OUTDRIV)
/**
* @}
*/
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
* @{
*/
#define SAI_MASTERDIVIDER_ENABLE ((uint32_t)0x00000000U)
#define SAI_MASTERDIVIDER_DISABLE ((uint32_t)SAI_xCR1_NOMCK)
/**
* @}
*/
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
* @{
*/
#define SAI_FS_STARTFRAME ((uint32_t)0x00000000U)
#define SAI_FS_CHANNEL_IDENTIFICATION ((uint32_t)SAI_xFRCR_FSDEF)
/**
* @}
*/
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
* @{
*/
#define SAI_FS_ACTIVE_LOW ((uint32_t)0x00000000U)
#define SAI_FS_ACTIVE_HIGH ((uint32_t)SAI_xFRCR_FSPOL)
/**
* @}
*/
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
* @{
*/
#define SAI_FS_FIRSTBIT ((uint32_t)0x00000000U)
#define SAI_FS_BEFOREFIRSTBIT ((uint32_t)SAI_xFRCR_FSOFF)
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
* @{
*/
#define SAI_SLOTSIZE_DATASIZE ((uint32_t)0x00000000U)
#define SAI_SLOTSIZE_16B ((uint32_t)SAI_xSLOTR_SLOTSZ_0)
#define SAI_SLOTSIZE_32B ((uint32_t)SAI_xSLOTR_SLOTSZ_1)
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
* @{
*/
#define SAI_SLOT_NOTACTIVE ((uint32_t)0x00000000U)
#define SAI_SLOTACTIVE_0 ((uint32_t)0x00000001U)
#define SAI_SLOTACTIVE_1 ((uint32_t)0x00000002U)
#define SAI_SLOTACTIVE_2 ((uint32_t)0x00000004U)
#define SAI_SLOTACTIVE_3 ((uint32_t)0x00000008U)
#define SAI_SLOTACTIVE_4 ((uint32_t)0x00000010U)
#define SAI_SLOTACTIVE_5 ((uint32_t)0x00000020U)
#define SAI_SLOTACTIVE_6 ((uint32_t)0x00000040U)
#define SAI_SLOTACTIVE_7 ((uint32_t)0x00000080U)
#define SAI_SLOTACTIVE_8 ((uint32_t)0x00000100U)
#define SAI_SLOTACTIVE_9 ((uint32_t)0x00000200U)
#define SAI_SLOTACTIVE_10 ((uint32_t)0x00000400U)
#define SAI_SLOTACTIVE_11 ((uint32_t)0x00000800U)
#define SAI_SLOTACTIVE_12 ((uint32_t)0x00001000U)
#define SAI_SLOTACTIVE_13 ((uint32_t)0x00002000U)
#define SAI_SLOTACTIVE_14 ((uint32_t)0x00004000U)
#define SAI_SLOTACTIVE_15 ((uint32_t)0x00008000U)
#define SAI_SLOTACTIVE_ALL ((uint32_t)0x0000FFFFU)
/**
* @}
*/
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
* @{
*/
#define SAI_STEREOMODE ((uint32_t)0x00000000U)
#define SAI_MONOMODE ((uint32_t)SAI_xCR1_MONO)
/**
* @}
*/
/** @defgroup SAI_TRIState_Management SAI TRIState Management
* @{
*/
#define SAI_OUTPUT_NOTRELEASED ((uint32_t)0x00000000U)
#define SAI_OUTPUT_RELEASED ((uint32_t)SAI_xCR2_TRIS)
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
* @{
*/
#define SAI_FIFOTHRESHOLD_EMPTY ((uint32_t)0x00000000U)
#define SAI_FIFOTHRESHOLD_1QF ((uint32_t)(SAI_xCR2_FTH_0))
#define SAI_FIFOTHRESHOLD_HF ((uint32_t)(SAI_xCR2_FTH_1))
#define SAI_FIFOTHRESHOLD_3QF ((uint32_t)(SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0))
#define SAI_FIFOTHRESHOLD_FULL ((uint32_t)(SAI_xCR2_FTH_2))
/**
* @}
*/
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
* @{
*/
#define SAI_NOCOMPANDING ((uint32_t)0x00000000U)
#define SAI_ULAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1))
#define SAI_ALAW_1CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0))
#define SAI_ULAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_CPL))
#define SAI_ALAW_2CPL_COMPANDING ((uint32_t)(SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL))
/**
* @}
*/
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
* @{
*/
#define SAI_ZERO_VALUE ((uint32_t)0x00000000U)
#define SAI_LAST_SENT_VALUE ((uint32_t)SAI_xCR2_MUTEVAL)
/**
* @}
*/
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
* @{
*/
#define SAI_IT_OVRUDR ((uint32_t)SAI_xIMR_OVRUDRIE)
#define SAI_IT_MUTEDET ((uint32_t)SAI_xIMR_MUTEDETIE)
#define SAI_IT_WCKCFG ((uint32_t)SAI_xIMR_WCKCFGIE)
#define SAI_IT_FREQ ((uint32_t)SAI_xIMR_FREQIE)
#define SAI_IT_CNRDY ((uint32_t)SAI_xIMR_CNRDYIE)
#define SAI_IT_AFSDET ((uint32_t)SAI_xIMR_AFSDETIE)
#define SAI_IT_LFSDET ((uint32_t)SAI_xIMR_LFSDETIE)
/**
* @}
*/
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
* @{
*/
#define SAI_FLAG_OVRUDR ((uint32_t)SAI_xSR_OVRUDR)
#define SAI_FLAG_MUTEDET ((uint32_t)SAI_xSR_MUTEDET)
#define SAI_FLAG_WCKCFG ((uint32_t)SAI_xSR_WCKCFG)
#define SAI_FLAG_FREQ ((uint32_t)SAI_xSR_FREQ)
#define SAI_FLAG_CNRDY ((uint32_t)SAI_xSR_CNRDY)
#define SAI_FLAG_AFSDET ((uint32_t)SAI_xSR_AFSDET)
#define SAI_FLAG_LFSDET ((uint32_t)SAI_xSR_LFSDET)
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
* @{
*/
#define SAI_FIFOSTATUS_EMPTY ((uint32_t)0x00000000U)
#define SAI_FIFOSTATUS_LESS1QUARTERFULL ((uint32_t)0x00010000U)
#define SAI_FIFOSTATUS_1QUARTERFULL ((uint32_t)0x00020000U)
#define SAI_FIFOSTATUS_HALFFULL ((uint32_t)0x00030000U)
#define SAI_FIFOSTATUS_3QUARTERFULL ((uint32_t)0x00040000U)
#define SAI_FIFOSTATUS_FULL ((uint32_t)0x00050000U)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SAI_Exported_Macros SAI Exported Macros
* @brief macros to handle interrupts and specific configurations
* @{
*/
/** @brief Reset SAI handle state.
* @param __HANDLE__ specifies the SAI Handle.
* @retval None
*/
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
/** @brief Enable or disable the specified SAI interrupts.
* @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
* @arg SAI_IT_FREQ: FIFO request interrupt enable
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
* @retval None
*/
#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SAI interrupt source is enabled or not.
* @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__ specifies the SAI interrupt source to check.
* This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
* @arg SAI_IT_FREQ: FIFO request interrupt enable
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SAI flag is set or not.
* @param __HANDLE__ specifies the SAI Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
* @arg SAI_FLAG_MUTEDET: Mute detection flag.
* @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
* @arg SAI_FLAG_FREQ: FIFO request flag.
* @arg SAI_FLAG_CNRDY: Codec not ready flag.
* @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
* @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified SAI pending flag.
* @param __HANDLE__ specifies the SAI Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
* @arg SAI_FLAG_MUTEDET: Clear Mute detection
* @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
* @arg SAI_FLAG_FREQ: Clear FIFO request
* @arg SAI_FLAG_CNRDY: Clear Codec not ready
* @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
* @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
*
* @retval None
*/
#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
/**
* @}
*/
/* Include SAI HAL Extension module */
#include "stm32h7xx_hal_sai_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SAI_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup SAI_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DeInit (SAI_HandleTypeDef *hsai);
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
/**
* @}
*/
/* I/O operation functions ***************************************************/
/** @addtogroup SAI_Exported_Functions_Group2
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
/* Abort function */
HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
/* Mute management */
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
/**
* @}
*/
/** @addtogroup SAI_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup SAI_Private_Macros
* @{
*/
#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
((PROTOCOL) == SAI_PCM_LONG) ||\
((PROTOCOL) == SAI_PCM_SHORT))
#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 4U))
#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
(((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE | \
SAI_PDM_CLOCK3_ENABLE | SAI_PDM_CLOCK4_ENABLE)) == 0U))
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
((MODE) == SAI_MODEMASTER_RX) || \
((MODE) == SAI_MODESLAVE_TX) || \
((MODE) == SAI_MODESLAVE_RX))
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
((PROTOCOL) == SAI_AC97_PROTOCOL) || \
((PROTOCOL) == SAI_SPDIF_PROTOCOL))
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
((DATASIZE) == SAI_DATASIZE_10) || \
((DATASIZE) == SAI_DATASIZE_16) || \
((DATASIZE) == SAI_DATASIZE_20) || \
((DATASIZE) == SAI_DATASIZE_24) || \
((DATASIZE) == SAI_DATASIZE_32))
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
((BIT) == SAI_FIRSTBIT_LSB))
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
((SYNCHRO) == SAI_SYNCHRONOUS) || \
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63)
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
((VALUE) == SAI_LAST_SENT_VALUE))
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
((MODE) == SAI_ALAW_2CPL_COMPANDING))
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
((STATE) == SAI_OUTPUT_RELEASED))
#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
((MODE) == SAI_STEREOMODE))
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1 <= (NUMBER)) && ((NUMBER) <= 16))
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
((SIZE) == SAI_SLOTSIZE_16B) || \
((SIZE) == SAI_SLOTSIZE_32B))
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24)
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
((POLARITY) == SAI_FS_ACTIVE_HIGH))
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63)
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8 <= (LENGTH)) && ((LENGTH) <= 256))
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1 <= (LENGTH)) && ((LENGTH) <= 128))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SAI_Private_Functions SAI Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SAI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai_ex.h
+130
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@@ -0,0 +1,130 @@
/**
******************************************************************************
* @file stm32h7xx_hal_sai_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SAI HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SAI_EX_H
#define __STM32H7xx_HAL_SAI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SAIEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SAIEx_Exported_Types SAIEx Exported Types
* @{
*/
/**
* @brief PDM microphone delay structure definition
*/
typedef struct
{
uint32_t MicPair; /*!< Specifies which pair of microphones is selected.
This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone.
This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone.
This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
}SAIEx_PdmMicDelayParamTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
* @{
*/
/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
* @{
*/
#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SAI_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h
+739
View File
@@ -0,0 +1,739 @@
/**
******************************************************************************
* @file stm32h7xx_hal_sd.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SD_H
#define __STM32H7xx_HAL_SD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_sdmmc.h"
#include "stm32h7xx_ll_delayblock.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SD
* @brief SD HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SD_Exported_Types SD Exported Types
* @{
*/
/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure
* @{
*/
typedef enum
{
HAL_SD_STATE_RESET = ((uint32_t)0x00000000U), /*!< SD not yet initialized or disabled */
HAL_SD_STATE_READY = ((uint32_t)0x00000001U), /*!< SD initialized and ready for use */
HAL_SD_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< SD Timeout state */
HAL_SD_STATE_BUSY = ((uint32_t)0x00000003U), /*!< SD process ongoing */
HAL_SD_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< SD Programming State */
HAL_SD_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< SD Receinving State */
HAL_SD_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< SD Transfert State */
HAL_SD_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< SD is in error state */
}HAL_SD_StateTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
* @{
*/
typedef enum
{
HAL_SD_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
HAL_SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
HAL_SD_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
HAL_SD_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
HAL_SD_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
HAL_SD_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
HAL_SD_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
HAL_SD_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
HAL_SD_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
}HAL_SD_CardStateTypedef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition
* @{
*/
#define SD_InitTypeDef SDMMC_InitTypeDef
#define SD_TypeDef SDMMC_TypeDef
/**
* @brief SD Card Information Structure definition
*/
typedef struct
{
uint32_t CardType; /*!< Specifies the card Type */
uint32_t CardVersion; /*!< Specifies the card version */
uint32_t Class; /*!< Specifies the class of the card class */
uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
uint32_t BlockSize; /*!< Specifies one block size in bytes */
uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
uint32_t CardSpeed; /*!< Specifies the card Speed */
}HAL_SD_CardInfoTypeDef;
/**
* @brief SD handle Structure definition
*/
typedef struct
{
SD_TypeDef *Instance; /*!< SD registers base address */
SD_InitTypeDef Init; /*!< SD required parameters */
HAL_LockTypeDef Lock; /*!< SD locking object */
uint32_t *pTxBuffPtr; /*!< Pointer to SD Tx transfer Buffer */
uint32_t TxXferSize; /*!< SD Tx Transfer size */
uint32_t *pRxBuffPtr; /*!< Pointer to SD Rx transfer Buffer */
uint32_t RxXferSize; /*!< SD Rx Transfer size */
__IO uint32_t Context; /*!< SD transfer context */
__IO HAL_SD_StateTypeDef State; /*!< SD card State */
__IO uint32_t ErrorCode; /*!< SD Card Error codes */
HAL_SD_CardInfoTypeDef SdCard; /*!< SD Card information */
uint32_t CSD[4]; /*!< SD card specific data table */
uint32_t CID[4]; /*!< SD card identification number table */
}SD_HandleTypeDef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register
* @{
*/
typedef struct
{
__IO uint8_t CSDStruct; /*!< CSD structure */
__IO uint8_t SysSpecVersion; /*!< System specification version */
__IO uint8_t Reserved1; /*!< Reserved */
__IO uint8_t TAAC; /*!< Data read access time 1 */
__IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
__IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
__IO uint16_t CardComdClasses; /*!< Card command classes */
__IO uint8_t RdBlockLen; /*!< Max. read data block length */
__IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
__IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
__IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
__IO uint8_t DSRImpl; /*!< DSR implemented */
__IO uint8_t Reserved2; /*!< Reserved */
__IO uint32_t DeviceSize; /*!< Device Size */
__IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
__IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
__IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
__IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
__IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
__IO uint8_t EraseGrSize; /*!< Erase group size */
__IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
__IO uint8_t WrProtectGrSize; /*!< Write protect group size */
__IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
__IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
__IO uint8_t WrSpeedFact; /*!< Write speed factor */
__IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
__IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
__IO uint8_t Reserved3; /*!< Reserved */
__IO uint8_t ContentProtectAppli; /*!< Content protection application */
__IO uint8_t FileFormatGrouop; /*!< File format group */
__IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
__IO uint8_t PermWrProtect; /*!< Permanent write protection */
__IO uint8_t TempWrProtect; /*!< Temporary write protection */
__IO uint8_t FileFormat; /*!< File format */
__IO uint8_t ECC; /*!< ECC code */
__IO uint8_t CSD_CRC; /*!< CSD CRC */
__IO uint8_t Reserved4; /*!< Always 1 */
}HAL_SD_CardCSDTypedef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register
* @{
*/
typedef struct
{
__IO uint8_t ManufacturerID; /*!< Manufacturer ID */
__IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
__IO uint32_t ProdName1; /*!< Product Name part1 */
__IO uint8_t ProdName2; /*!< Product Name part2 */
__IO uint8_t ProdRev; /*!< Product Revision */
__IO uint32_t ProdSN; /*!< Product Serial Number */
__IO uint8_t Reserved1; /*!< Reserved1 */
__IO uint16_t ManufactDate; /*!< Manufacturing Date */
__IO uint8_t CID_CRC; /*!< CID CRC */
__IO uint8_t Reserved2; /*!< Always 1 */
}HAL_SD_CardCIDTypedef;
/**
* @}
*/
/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13
* @{
*/
typedef struct
{
__IO uint8_t DataBusWidth; /*!< Shows the currently defined data bus width */
__IO uint8_t SecuredMode; /*!< Card is in secured mode of operation */
__IO uint16_t CardType; /*!< Carries information about card type */
__IO uint32_t ProtectedAreaSize; /*!< Carries information about the capacity of protected area */
__IO uint8_t SpeedClass; /*!< Carries information about the speed class of the card */
__IO uint8_t PerformanceMove; /*!< Carries information about the card's performance move */
__IO uint8_t AllocationUnitSize; /*!< Carries information about the card's allocation unit size */
__IO uint16_t EraseSize; /*!< Determines the number of AUs to be erased in one operation */
__IO uint8_t EraseTimeout; /*!< Determines the timeout for any number of AU erase */
__IO uint8_t EraseOffset; /*!< Carries information about the erase offset */
}HAL_SD_CardStatusTypedef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SD_Exported_Constants Exported Constants
* @{
*/
#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition
* @{
*/
#define HAL_SD_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
#define HAL_SD_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
#define HAL_SD_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
#define HAL_SD_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
#define HAL_SD_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
#define HAL_SD_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
#define HAL_SD_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
#define HAL_SD_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
#define HAL_SD_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
number of transferred bytes does not match the block length */
#define HAL_SD_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
#define HAL_SD_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
#define HAL_SD_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
command or if there was an attempt to access a locked card */
#define HAL_SD_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
#define HAL_SD_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
#define HAL_SD_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
#define HAL_SD_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
#define HAL_SD_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
#define HAL_SD_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
#define HAL_SD_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
#define HAL_SD_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
#define HAL_SD_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
of erase sequence command was received */
#define HAL_SD_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
#define HAL_SD_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
#define HAL_SD_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
#define HAL_SD_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
#define HAL_SD_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
#define HAL_SD_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
#define HAL_SD_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout Error */
/**
* @}
*/
/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration
* @{
*/
#define SD_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
#define SD_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
#define SD_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
#define SD_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
#define SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
#define SD_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
#define SD_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
/**
* @}
*/
/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards
* @{
*/
#define CARD_NORMAL_SPEED ((uint32_t)0x00000000U) /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01 */
#define CARD_HIGH_SPEED ((uint32_t)0x00000100U) /*!< High Speed Card <25Mo/s , Spec version 2.00 */
#define CARD_ULTRA_HIGH_SPEED ((uint32_t)0x00000200U) /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
and <104Mo/s for SDR104, Spec version 3.01 */
#define CARD_SDSC ((uint32_t)0x00000000U) /*!< SD Standard Capacity <2Go */
#define CARD_SDHC_SDXC ((uint32_t)0x00000001U) /*!< SD High Capacity <32Go, SD Extended Capacity <2To */
#define CARD_SECURED ((uint32_t)0x00000003U)
/**
* @}
*/
/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version
* @{
*/
#define CARD_V1_X ((uint32_t)0x00000000U)
#define CARD_V2_X ((uint32_t)0x00000001U)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SD_Exported_macros SD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
/**
* @brief Enable the SD device interrupt.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Disable the SD device interrupt.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Check whether the specified SD flag is set or not.
* @param __HANDLE__: SD Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_CPSMACT: Command path state machine active
* @arg SDMMC_FLAG_DPSMACT: Data path state machine active
* @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
* @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
* @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
* @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
* @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
* @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
* @arg SDMMC_FLAG_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
* @retval The new state of SD FLAG (SET or RESET).
*/
#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Clear the SD's pending flags.
* @param __HANDLE__: SD Handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
* @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
* @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
* @arg SDMMC_FLAG_DTIMEOUT: Data timeout
* @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
* @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
* @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
* @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
* @arg SDMMC_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero)
* @arg SDMMC_FLAG_DHOLD: Data transfer Hold
* @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
* @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12
* @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected
* @arg SDMMC_FLAG_SDIOIT: SDIO interrupt received
* @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received
* @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout
* @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion
* @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure
* @arg SDMMC_FLAG_IDMATE: IDMA transfer error
* @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete
* @retval None
*/
#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
/**
* @brief Check whether the specified SD interrupt has occurred or not.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
* This parameter can be one of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_DPSMACT: Data path state machine active interrupt
* @arg SDMMC_IT_CPSMACT: Command path state machine active interrupt
* @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
* @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
* @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
* @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
* @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
* @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
* @arg SDMMC_IT_BUSYD0: Inverted value of SDMMC_D0 line (Busy)
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval The new state of SD IT (SET or RESET).
*/
#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @brief Clear the SD's interrupt pending bits.
* @param __HANDLE__: SD Handle
* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
* This parameter can be one or a combination of the following values:
* @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
* @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
* @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
* @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
* @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
* @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
* @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
* @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
* @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt
* @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt
* @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
* @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt
* @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt
* @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt
* @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt
* @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
* @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt
* @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt
* @arg SDMMC_IT_IDMATE: IDMA transfer error interrupt
* @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt
* @retval None
*/
#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
/**
* @}
*/
/* Include SD HAL Extension module */
#include "stm32h7xx_hal_sd_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup SD_Exported_Functions SD Exported Functions
* @{
*/
/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
/* Non-Blocking mode: IT */
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
/* Callback in non blocking modes (DMA) */
void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
/* Callback to switch in 1.8V mode */
void HAL_SD_DriveTransciver_1_8V_Callback(FlagStatus status);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group4 SD card related functions
* @{
*/
HAL_StatusTypeDef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID);
HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD);
HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus);
HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions
* @{
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
/**
* @}
*/
/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
* @{
*/
HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup SD_Private_Types SD Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup SD_Private_Defines SD Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup SD_Private_Variables SD Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SD_Private_Constants SD Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SD_Private_Macros SD Private Macros
* @{
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SD_Private_Functions SD Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SD_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_sd_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SD HAL extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SD_EX_H
#define __STM32H7xx_HAL_SD_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SDEx
* @brief SD HAL extended module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SDEx_Exported_Types SDEx Exported Types
* @{
*/
/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure
* @{
*/
typedef enum
{
SD_DMA_BUFFER0 = 0x00U, /*!< selects SD internal DMA Buffer 0 */
SD_DMA_BUFFER1 = 0x01U, /*!< selects SD internal DMA Buffer 1 */
}HAL_SDEx_DMABuffer_MemoryTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDEx_Exported_Functions SDEx Exported Functions
* @{
*/
/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions
* @{
*/
HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SDEx_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h
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/**
******************************************************************************
* @file stm32h7xx_hal_sdram.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SDRAM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SDRAM_H
#define __STM32H7xx_HAL_SDRAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_fmc.h"
#include "stm32h7xx_hal_mdma.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SDRAM
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Types SDRAM Exported Types
* @{
*/
/**
* @brief HAL SDRAM State structure definition
*/
typedef enum
{
HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */
HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */
HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */
HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */
HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */
HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */
}HAL_SDRAM_StateTypeDef;
/**
* @brief SDRAM handle Structure definition
*/
typedef struct
{
FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
__IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
HAL_LockTypeDef Lock; /*!< SDRAM locking object */
MDMA_HandleTypeDef *hmdma; /*!< Pointer MDMA handler */
}SDRAM_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros
* @{
*/
/** @brief Reset SDRAM handle state
* @param __HANDLE__: specifies the SDRAM handle.
* @retval None
*/
#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions
* @{
*/
/** @addtogroup SDRAM_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions *********************************/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
/**
* @}
*/
/** @addtogroup SDRAM_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
/**
* @}
*/
/** @addtogroup SDRAM_Exported_Functions_Group3
* @{
*/
/* SDRAM Control functions *****************************************************/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
/**
* @}
*/
/** @addtogroup SDRAM_Exported_Functions_Group4
* @{
*/
/* SDRAM State functions ********************************************************/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SDRAM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_smartcard_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SMARTCARD_EX_H
#define __STM32H7xx_HAL_SMARTCARD_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SMARTCARDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
* @{
*/
/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
* @{
*/
#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
* @{
*/
#define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /*!< No advanced feature initialization */
#define SMARTCARD_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /*!< TX pin active level inversion */
#define SMARTCARD_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /*!< RX pin active level inversion */
#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /*!< Binary data inversion */
#define SMARTCARD_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /*!< TX/RX pins swap */
#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /*!< RX overrun disable */
#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /*!< DMA disable on Reception Error */
#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /*!< Most significant bit sent/received first */
#define SMARTCARD_ADVFEATURE_TXCOMPLETION ((uint32_t)0x00000100) /*!< TX completion indication before of after guard time */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
#define SMARTCARD_FLAG_TXE USART_ISR_TXE /*!< SMARTCARD transmit data register empty */
#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE /*!< SMARTCARD read data register not empty */
#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */
#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */
#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Fullflag */
#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 000ZZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5 bits)
* - XX : Interrupt source register (2 bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZZ : Flag position in the ISR register(5 bits)
* @{
*/
#define SMARTCARD_IT_PE ((uint16_t)0x0028) /*!< SMARTCARD parity error interruption */
#define SMARTCARD_IT_TXE ((uint16_t)0x0727) /*!< SMARTCARD transmit data register empty interruption */
#define SMARTCARD_IT_TC ((uint16_t)0x0626) /*!< SMARTCARD transmission complete interruption */
#define SMARTCARD_IT_RXNE ((uint16_t)0x0525) /*!< SMARTCARD read data register not empty interruption */
#define SMARTCARD_IT_IDLE ((uint16_t)0x0424) /*!< SMARTCARD idle line detection interruption */
#define SMARTCARD_IT_ERR ((uint16_t)0x0060) /*!< SMARTCARD error interruption */
#define SMARTCARD_IT_ORE ((uint16_t)0x0300) /*!< SMARTCARD overrun error interruption */
#define SMARTCARD_IT_NE ((uint16_t)0x0200) /*!< SMARTCARD noise error interruption */
#define SMARTCARD_IT_FE ((uint16_t)0x0100) /*!< SMARTCARD frame error interruption */
#define SMARTCARD_IT_EOB ((uint16_t)0x0C3B) /*!< SMARTCARD end of block interruption */
#define SMARTCARD_IT_RTO ((uint16_t)0x0B3A) /*!< SMARTCARD receiver timeout interruption */
#define SMARTCARD_IT_RXFF ((uint16_t)0x183F)
#define SMARTCARD_IT_TXFE ((uint16_t)0x173E)
#define SMARTCARD_IT_RXFT ((uint16_t)0x187C)
#define SMARTCARD_IT_TXFT ((uint16_t)0x1B77)
#define SMARTCARD_IT_TCBGT ((uint16_t)0x1978) /*!< SMARTCARD transmission complete before guard time completion interruption */
/**
* @}
*/
/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
* @{
*/
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
#define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< SMARTCARD noise detected clear flag */
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< SMARTCARD TXFIFO empty clear flag */
#define SMARTCARD_CLEAR_UDRCF USART_ICR_UDRCF /*!< SMARTCARD UnderRun Error Clear Flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
* @{
*/
/** @brief Report the SMARTCARD clock source.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* @param __CLOCKSOURCE__: output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART2CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART2CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART3CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART3CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART6CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q; \
break; \
case RCC_USART6CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
} \
} \
} while(0)
/** @brief Set the Transmission Completion flag
* @param __HANDLE__: specifies the SMARTCARD Handle.
* @retval None
*/
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
do { \
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
{ \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} \
else \
{ \
assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
} \
} while(0)
/** @brief Return the transmission completion flag.
* @param __HANDLE__: specifies the SMARTCARD Handle.
* @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
* @retval Transmission completion flag
*/
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
(((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
/**
* @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
* @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
*/
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) ||\
((__TXCOMPLETE__) == SMARTCARD_TC))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/* IO operation methods *******************************************************/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ***********************************************/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SMARTCARD_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smbus.h
+696
View File
@@ -0,0 +1,696 @@
/**
******************************************************************************
* @file stm32h7xx_hal_smbus.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SMBUS_H
#define __STM32H7xx_HAL_SMBUS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SMBUS
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
* @{
*/
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
* @brief SMBUS Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
This parameter calculated by referring to SMBUS initialization
section in Reference manual */
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
This parameter can be a value of @ref SMBUS_Analog_Filter */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
This parameter can be a value of @ref SMBUS_addressing_mode */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref SMBUS_nostretch_mode */
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
(Enable bits and different timeout values)
This parameter calculated by referring to SMBUS initialization
section in Reference manual */
} SMBUS_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_definition HAL state definition
* @brief HAL State definition
* @{
*/
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
*/
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
* @brief SMBUS Error Code definition
* @{
*/
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
/**
* @}
*/
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
* @brief SMBUS handle Structure definition
* @{
*/
typedef struct
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
uint16_t XferSize; /*!< SMBUS transfer size */
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
__IO uint32_t State; /*!< SMBUS communication state */
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
}SMBUS_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
* @{
*/
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
* @{
*/
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
* @{
*/
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup SMBUS_own_address2_masks SMBUS own address2 masks
* @{
*/
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
* @{
*/
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
* @{
*/
#define SMBUS_PEC_DISABLE (0x00000000U)
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
/**
* @}
*/
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
* @{
*/
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
/**
* @}
*/
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
* @{
*/
#define SMBUS_SOFTEND_MODE (0x00000000U)
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
/**
* @}
*/
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
* @{
*/
#define SMBUS_NO_STARTSTOP (0x00000000U)
#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
* @{
*/
/* List of XferOptions in usage of :
* 1- Restart condition when direction change
* 2- No Restart condition in other use cases
*/
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
/**
* @}
*/
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
* @brief SMBUS Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
#define SMBUS_IT_TCI I2C_CR1_TCIE
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
/**
* @}
*/
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
* @brief Flag definition
* Elements values convention: 0xXXXXYYYY
* - XXXXXXXX : Flag mask
* @{
*/
#define SMBUS_FLAG_TXE I2C_ISR_TXE
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define SMBUS_FLAG_AF I2C_ISR_NACKF
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define SMBUS_FLAG_TC I2C_ISR_TC
#define SMBUS_FLAG_TCR I2C_ISR_TCR
#define SMBUS_FLAG_BERR I2C_ISR_BERR
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define SMBUS_FLAG_OVR I2C_ISR_OVR
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define SMBUS_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
* @{
*/
/** @brief Reset SMBUS handle state.
* @param __HANDLE__: specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__: specifies the SMBUS Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg SMBUS_IT_ERRI: Errors interrupt enable
* @arg SMBUS_IT_TCI: Transfer complete interrupt enable
* @arg SMBUS_IT_STOPI: STOP detection interrupt enable
* @arg SMBUS_IT_NACKI: NACK received interrupt enable
* @arg SMBUS_IT_ADDRI: Address match interrupt enable
* @arg SMBUS_IT_RXI: RX interrupt enable
* @arg SMBUS_IT_TXI: TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified SMBUS interrupts.
* @param __HANDLE__: specifies the SMBUS Handle.
* @param __INTERRUPT__: specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg SMBUS_IT_ERRI: Errors interrupt enable
* @arg SMBUS_IT_TCI: Transfer complete interrupt enable
* @arg SMBUS_IT_STOPI: STOP detection interrupt enable
* @arg SMBUS_IT_NACKI: NACK received interrupt enable
* @arg SMBUS_IT_ADDRI: Address match interrupt enable
* @arg SMBUS_IT_RXI: RX interrupt enable
* @arg SMBUS_IT_TXI: TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
* @param __HANDLE__: specifies the SMBUS Handle.
* @param __INTERRUPT__: specifies the SMBUS interrupt source to check.
* This parameter can be one of the following values:
* @arg SMBUS_IT_ERRI: Errors interrupt enable
* @arg SMBUS_IT_TCI: Transfer complete interrupt enable
* @arg SMBUS_IT_STOPI: STOP detection interrupt enable
* @arg SMBUS_IT_NACKI: NACK received interrupt enable
* @arg SMBUS_IT_ADDRI: Address match interrupt enable
* @arg SMBUS_IT_RXI: RX interrupt enable
* @arg SMBUS_IT_TXI: TX interrupt enable
*
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SMBUS flag is set or not.
* @param __HANDLE__: specifies the SMBUS Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SMBUS_FLAG_TXE: Transmit data register empty
* @arg SMBUS_FLAG_TXIS: Transmit interrupt status
* @arg SMBUS_FLAG_RXNE: Receive data register not empty
* @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
* @arg SMBUS_FLAG_AF: NACK received flag
* @arg SMBUS_FLAG_STOPF: STOP detection flag
* @arg SMBUS_FLAG_TC: Transfer complete (master mode)
* @arg SMBUS_FLAG_TCR: Transfer complete reload
* @arg SMBUS_FLAG_BERR: Bus error
* @arg SMBUS_FLAG_ARLO: Arbitration lost
* @arg SMBUS_FLAG_OVR: Overrun/Underrun
* @arg SMBUS_FLAG_PECERR: PEC error in reception
* @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
* @arg SMBUS_FLAG_ALERT: SMBus alert
* @arg SMBUS_FLAG_BUSY: Bus busy
* @arg SMBUS_FLAG_DIR: Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__: specifies the SMBUS Handle.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg SMBUS_FLAG_ADDR: Address matched (slave mode)
* @arg SMBUS_FLAG_AF: NACK received flag
* @arg SMBUS_FLAG_STOPF: STOP detection flag
* @arg SMBUS_FLAG_BERR: Bus error
* @arg SMBUS_FLAG_ARLO: Arbitration lost
* @arg SMBUS_FLAG_OVR: Overrun/Underrun
* @arg SMBUS_FLAG_PECERR: PEC error in reception
* @arg SMBUS_FLAG_TIMEOUT: Timeout or Tlow detection flag
* @arg SMBUS_FLAG_ALERT: SMBus alert
*
* @retval None
*/
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Enable the specified SMBUS peripheral.
* @param __HANDLE__: specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified SMBUS peripheral.
* @param __HANDLE__: specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
* @param __HANDLE__: specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
* @{
*/
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
((MASK) == SMBUS_OA2_MASK01) || \
((MASK) == SMBUS_OA2_MASK02) || \
((MASK) == SMBUS_OA2_MASK03) || \
((MASK) == SMBUS_OA2_MASK04) || \
((MASK) == SMBUS_OA2_MASK05) || \
((MASK) == SMBUS_OA2_MASK06) || \
((MASK) == SMBUS_OA2_MASK07))
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
((CALL) == SMBUS_GENERALCALL_ENABLE))
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
((PEC) == SMBUS_PEC_ENABLE))
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
((MODE) == SMBUS_AUTOEND_MODE) || \
((MODE) == SMBUS_SOFTEND_MODE) || \
((MODE) == SMBUS_SENDPEC_MODE) || \
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
((REQUEST) == SMBUS_GENERATE_START_READ) || \
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
((REQUEST) == SMBUS_NO_STARTSTOP))
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \
IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR)
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
*/
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
* @{
*/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
* @{
*/
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
/* Private functions are defined in stm32h7xx_hal_smbus.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SMBUS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spdifrx.h
+570
View File
@@ -0,0 +1,570 @@
/**
******************************************************************************
* @file stm32h7xx_hal_spdifrx.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SPDIFRX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SPDIFRX_H
#define __STM32H7xx_HAL_SPDIFRX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
#if defined (SPDIFRX)
/** @addtogroup SPDIFRX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types
* @{
*/
/**
* @brief SPDIFRX Init structure definition
*/
typedef struct
{
uint32_t InputSelection; /*!< Specifies the SPDIF input selection.
This parameter can be a value of @ref SPDIFRX_Input_Selection */
uint32_t Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
This parameter can be a value of @ref SPDIFRX_Max_Retries */
uint32_t WaitForActivity; /*!< Specifies the wait for activity on SPDIF selected input.
This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
uint32_t ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
This parameter can be a value of @ref SPDIFRX_Channel_Selection */
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
This parameter can be a value of @ref SPDIFRX_Data_Format */
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_V_Mask */
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
FunctionalState SymbolClockGen; /*!< Enable/Disable the SPDIFRX Symbol Clock generation.
This parameter can be set to Enable or Disable */
FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.
This parameter can be set to Enable or Disable */
} SPDIFRX_InitTypeDef;
/**
* @brief SPDIFRX SetDataFormat structure definition
*/
typedef struct
{
uint32_t DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
This parameter can be a value of @ref SPDIFRX_Data_Format */
uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
uint32_t PreambleTypeMask; /*!< Specifies whether The preamble type bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PT_Mask */
uint32_t ChannelStatusMask; /*!< Specifies whether the channel status and user bits are copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */
uint32_t ValidityBitMask; /*!< Specifies whether the validity bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_V_Mask */
uint32_t ParityErrorMask; /*!< Specifies whether the parity error bit is copied or not into the received frame.
This parameter can be a value of @ref SPDIFRX_PE_Mask */
} SPDIFRX_SetDataFormatTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_SPDIFRX_STATE_RESET = 0x00U, /*!< SPDIFRX not yet initialized or disabled */
HAL_SPDIFRX_STATE_READY = 0x01U, /*!< SPDIFRX initialized and ready for use */
HAL_SPDIFRX_STATE_BUSY = 0x02U, /*!< SPDIFRX internal process is ongoing */
HAL_SPDIFRX_STATE_BUSY_RX = 0x03U, /*!< SPDIFRX internal Data Flow RX process is ongoing */
HAL_SPDIFRX_STATE_BUSY_CX = 0x04U, /*!< SPDIFRX internal Control Flow RX process is ongoing */
HAL_SPDIFRX_STATE_ERROR = 0x07U /*!< SPDIFRX error state */
} HAL_SPDIFRX_StateTypeDef;
/**
* @brief SPDIFRX handle Structure definition
*/
typedef struct
{
SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */
SPDIFRX_InitTypeDef Init; /* SPDIFRX communication parameters */
uint32_t *pRxBuffPtr; /* Pointer to SPDIFRX Rx transfer buffer */
uint32_t *pCsBuffPtr; /* Pointer to SPDIFRX Cx transfer buffer */
__IO uint16_t RxXferSize; /* SPDIFRX Rx transfer size */
__IO uint16_t RxXferCount; /* SPDIFRX Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
__IO uint16_t CsXferSize; /* SPDIFRX Rx transfer size */
__IO uint16_t CsXferCount; /* SPDIFRX Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received.
NbSamplesReceived = RxBufferSize-RxBufferCount) */
DMA_HandleTypeDef *hdmaCsRx; /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */
DMA_HandleTypeDef *hdmaDrRx; /* SPDIFRX Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /* SPDIFRX locking object */
__IO HAL_SPDIFRX_StateTypeDef State; /* SPDIFRX communication state */
__IO uint32_t ErrorCode; /* SPDIFRX Error code */
} SPDIFRX_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants
* @{
*/
/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code
* @{
*/
#define HAL_SPDIFRX_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_SPDIFRX_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
#define HAL_SPDIFRX_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */
#define HAL_SPDIFRX_ERROR_PE ((uint32_t)0x00000004U) /*!< Parity error */
#define HAL_SPDIFRX_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
#define HAL_SPDIFRX_ERROR_UNKNOWN ((uint32_t)0x00000010U) /*!< Unknown Error error */
/**
* @}
*/
/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
* @{
*/
#define SPDIFRX_INPUT_IN0 ((uint32_t)0x00000000U)
#define SPDIFRX_INPUT_IN1 ((uint32_t)0x00010000U)
#define SPDIFRX_INPUT_IN2 ((uint32_t)0x00020000U)
#define SPDIFRX_INPUT_IN3 ((uint32_t)0x00030000U)
/**
* @}
*/
/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries
* @{
*/
#define SPDIFRX_MAXRETRIES_NONE ((uint32_t)0x00000000U)
#define SPDIFRX_MAXRETRIES_3 ((uint32_t)0x00001000U)
#define SPDIFRX_MAXRETRIES_15 ((uint32_t)0x00002000U)
#define SPDIFRX_MAXRETRIES_63 ((uint32_t)0x00003000U)
/**
* @}
*/
/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
* @{
*/
#define SPDIFRX_WAITFORACTIVITY_OFF ((uint32_t)0x00000000U)
#define SPDIFRX_WAITFORACTIVITY_ON ((uint32_t)SPDIFRX_CR_WFA)
/**
* @}
*/
/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask
* @{
*/
#define SPDIFRX_PREAMBLETYPEMASK_OFF ((uint32_t)0x00000000U)
#define SPDIFRX_PREAMBLETYPEMASK_ON ((uint32_t)SPDIFRX_CR_PTMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_ChannelStatus_Mask SPDIFRX Channel Status Mask
* @{
*/
#define SPDIFRX_CHANNELSTATUS_OFF ((uint32_t)0x00000000U) /* The channel status and user bits are copied into the SPDIF_DR */
#define SPDIFRX_CHANNELSTATUS_ON ((uint32_t)SPDIFRX_CR_CUMSK) /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/
/**
* @}
*/
/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask
* @{
*/
#define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U)
#define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_PE_Mask SPDIFRX Parity Error Mask
* @{
*/
#define SPDIFRX_PARITYERRORMASK_OFF ((uint32_t)0x00000000U)
#define SPDIFRX_PARITYERRORMASK_ON ((uint32_t)SPDIFRX_CR_PMSK)
/**
* @}
*/
/** @defgroup SPDIFRX_Channel_Selection SPDIFRX Channel Selection
* @{
*/
#define SPDIFRX_CHANNEL_A ((uint32_t)0x00000000U)
#define SPDIFRX_CHANNEL_B ((uint32_t)SPDIFRX_CR_CHSEL)
/**
* @}
*/
/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format
* @{
*/
#define SPDIFRX_DATAFORMAT_LSB ((uint32_t)0x00000000U)
#define SPDIFRX_DATAFORMAT_MSB ((uint32_t)0x00000010U)
#define SPDIFRX_DATAFORMAT_32BITS ((uint32_t)0x00000020U)
/**
* @}
*/
/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode
* @{
*/
#define SPDIFRX_STEREOMODE_DISABLE ((uint32_t)0x00000000U)
#define SPDIFRX_STEREOMODE_ENABLE ((uint32_t)SPDIFRX_CR_RXSTEO)
/**
* @}
*/
/** @defgroup SPDIFRX_State SPDIFRX State
* @{
*/
#define SPDIFRX_STATE_IDLE ((uint32_t)0xFFFFFFFCU)
#define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001U)
#define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
/**
* @}
*/
/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
* @{
*/
#define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
#define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
#define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
#define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
#define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
#define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
#define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
/**
* @}
*/
/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
* @{
*/
#define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
#define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
#define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
#define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
#define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
#define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
#define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
#define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
#define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros
* @{
*/
/** @brief Reset SPDIFRX handle state
* @param __HANDLE__: SPDIFRX handle.
* @retval None
*/
#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN)
/** @brief Disable the specified SPDIFRX peripheral (IDLE State).
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @retval None
*/
#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)
/** @brief Enable the specified SPDIFRX peripheral (SYNC State).
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @retval None
*/
#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)
/** @brief Enable the specified SPDIFRX peripheral (RCV State).
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @retval None
*/
#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)
/** @brief Enable or disable the specified SPDIFRX interrupts.
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
* @arg SPDIFRX_IT_CSRNE
* @arg SPDIFRX_IT_PERRIE
* @arg SPDIFRX_IT_OVRIE
* @arg SPDIFRX_IT_SBLKIE
* @arg SPDIFRX_IT_SYNCDIE
* @arg SPDIFRX_IT_IFEIE
* @retval None
*/
#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))
/** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_IT_RXNE
* @arg SPDIFRX_IT_CSRNE
* @arg SPDIFRX_IT_PERRIE
* @arg SPDIFRX_IT_OVRIE
* @arg SPDIFRX_IT_SBLKIE
* @arg SPDIFRX_IT_SYNCDIE
* @arg SPDIFRX_IT_IFEIE
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified SPDIFRX flag is set or not.
* @param __HANDLE__: specifies the SPDIFRX Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_RXNE
* @arg SPDIFRX_FLAG_CSRNE
* @arg SPDIFRX_FLAG_PERR
* @arg SPDIFRX_FLAG_OVR
* @arg SPDIFRX_FLAG_SBD
* @arg SPDIFRX_FLAG_SYNCD
* @arg SPDIFRX_FLAG_FERR
* @arg SPDIFRX_FLAG_SERR
* @arg SPDIFRX_FLAG_TERR
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.
* @param __HANDLE__: specifies the USART Handle.
* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg SPDIFRX_FLAG_PERR
* @arg SPDIFRX_FLAG_OVR
* @arg SPDIFRX_SR_SBD
* @arg SPDIFRX_SR_SYNCD
* @retval None
*/
#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPDIFRX_Exported_Functions
* @{
*/
/** @addtogroup SPDIFRX_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);
HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);
HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat);
/**
* @}
*/
/** @addtogroup SPDIFRX_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);
/**
* @}
*/
/** @addtogroup SPDIFRX_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif);
uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros
* @{
*/
#define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \
((INPUT) == SPDIFRX_INPUT_IN2) || \
((INPUT) == SPDIFRX_INPUT_IN3) || \
((INPUT) == SPDIFRX_INPUT_IN0))
#define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \
((RET) == SPDIFRX_MAXRETRIES_3) || \
((RET) == SPDIFRX_MAXRETRIES_15) || \
((RET) == SPDIFRX_MAXRETRIES_63))
#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \
((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))
#define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \
((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))
#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \
((VAL) == SPDIFRX_VALIDITYMASK_ON))
#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \
((VAL) == SPDIFRX_PARITYERRORMASK_ON))
#define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \
((CHANNEL) == SPDIFRX_CHANNEL_B))
#define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \
((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \
((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))
#define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \
((MODE) == SPDIFRX_STEREOMODE_ENABLE))
#define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \
((VAL) == SPDIFRX_CHANNELSTATUS_OFF))
#define IS_SYMBOL_CLOCK_GEN(VAL) (((VAL) == ENABLE) || ((VAL) == DISABLE))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SPDIFRX */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SPDIFRX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h
+985
View File
@@ -0,0 +1,985 @@
/**
******************************************************************************
* @file stm32h7xx_hal_spi.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SPI_H
#define __STM32H7xx_HAL_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Configuration Structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_Mode */
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
uint32_t DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_Data_Size */
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_Management */
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_Transmission */
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
This parameter can be a value of @ref SPI_TI_Mode */
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_CRC_Calculation */
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
CRC Length is only used with Data8 and Data16, not other data size
This parameter can be a value of @ref SPI_CRC_length */
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
This parameter can be a value of @ref SPI_NSSP_Mode
This mode is activated by the NSSP bit in the SPIx_CR2 register and
it takes effect only if the SPI interface is configured as Motorola SPI
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
CPOL setting is ignored). */
uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal (present on SS pin) is
considered as active one.
This parameter can be a value of @ref SPI_NSS_Polarity */
uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level.
This parameter can be a value of @ref SPI_Fifo_Threshold */
uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.
This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.
This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */
uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted
additionally between active edge of SS and first data transaction start in master mode.
This parameter can be a value of @ref SPI_Master_SS_Idleness */
uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between
two consecutive data frames in master mode
This parameter can be a value of @ref SPI_Master_InterData_Idleness */
uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode and automatic management
in order to avoid overrun condition.
This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/
uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state
This parameter can be a value of @ref SPI_Master_Keep_IO_State */
uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions
This parameter can be a value of @ref SPI_IO_Swap */
} SPI_InitTypeDef;
/**
* @brief HAL SPI State structure definition
*/
typedef enum
{
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
} HAL_SPI_StateTypeDef;
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< SPI registers base address */
SPI_InitTypeDef Init; /*!< SPI communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
__IO uint32_t ErrorCode; /*!< SPI Error code */
} SPI_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_FIFO_Type SPI FIFO Type
* @{
*/
#define SPI_LOWEND_FIFO_SIZE 8U
#define SPI_HIGHEND_FIFO_SIZE 16U
/**
* @}
*/
/** @defgroup SPI_Error_Code SPI Error Codes
* @{
*/
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
#define HAL_SPI_ERROR_UDR (0x00000080U) /*!< Underrun error */
#define HAL_SPI_ERROR_TIMEOUT (0x00000100U) /*!< Timeout error */
#define HAL_SPI_ERROR_UNKNOW (0x00000200U) /*!< Unknow error */
#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400U) /*!< Requested operation not supported */
/**
* @}
*/
/** @defgroup SPI_Mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE (0x00000000U)
#define SPI_MODE_MASTER SPI_CFG2_MASTER
/**
* @}
*/
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES (0x00000000U)
#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0
#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1
#define SPI_DIRECTION_1LINE SPI_CFG2_COMM
/**
* @}
*/
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
#define SPI_DATASIZE_4BIT (0x00000003U)
#define SPI_DATASIZE_5BIT (0x00000004U)
#define SPI_DATASIZE_6BIT (0x00000005U)
#define SPI_DATASIZE_7BIT (0x00000006U)
#define SPI_DATASIZE_8BIT (0x00000007U)
#define SPI_DATASIZE_9BIT (0x00000008U)
#define SPI_DATASIZE_10BIT (0x00000009U)
#define SPI_DATASIZE_11BIT (0x0000000AU)
#define SPI_DATASIZE_12BIT (0x0000000BU)
#define SPI_DATASIZE_13BIT (0x0000000CU)
#define SPI_DATASIZE_14BIT (0x0000000DU)
#define SPI_DATASIZE_15BIT (0x0000000EU)
#define SPI_DATASIZE_16BIT (0x0000000FU)
#define SPI_DATASIZE_17BIT (0x00000010U)
#define SPI_DATASIZE_18BIT (0x00000011U)
#define SPI_DATASIZE_19BIT (0x00000012U)
#define SPI_DATASIZE_20BIT (0x00000013U)
#define SPI_DATASIZE_21BIT (0x00000014U)
#define SPI_DATASIZE_22BIT (0x00000015U)
#define SPI_DATASIZE_23BIT (0x00000016U)
#define SPI_DATASIZE_24BIT (0x00000017U)
#define SPI_DATASIZE_25BIT (0x00000018U)
#define SPI_DATASIZE_26BIT (0x00000019U)
#define SPI_DATASIZE_27BIT (0x0000001AU)
#define SPI_DATASIZE_28BIT (0x0000001BU)
#define SPI_DATASIZE_29BIT (0x0000001CU)
#define SPI_DATASIZE_30BIT (0x0000001DU)
#define SPI_DATASIZE_31BIT (0x0000001EU)
#define SPI_DATASIZE_32BIT (0x0000001FU)
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW (0x00000000U)
#define SPI_POLARITY_HIGH SPI_CFG2_CPOL
/**
* @}
*/
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE (0x00000000U)
#define SPI_PHASE_2EDGE SPI_CFG2_CPHA
/**
* @}
*/
/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CFG2_SSM
#define SPI_NSS_HARD_INPUT (0x00000000U)
#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE
/**
* @}
*/
/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
* @{
*/
#define SPI_NSS_PULSE_DISABLE (0x00000000U)
#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define SPI_BAUDRATEPRESCALER_4 (0x10000000U)
#define SPI_BAUDRATEPRESCALER_8 (0x20000000U)
#define SPI_BAUDRATEPRESCALER_16 (0x30000000U)
#define SPI_BAUDRATEPRESCALER_32 (0x40000000U)
#define SPI_BAUDRATEPRESCALER_64 (0x50000000U)
#define SPI_BAUDRATEPRESCALER_128 (0x60000000U)
#define SPI_BAUDRATEPRESCALER_256 (0x70000000U)
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission
* @{
*/
#define SPI_FIRSTBIT_MSB (0x00000000U)
#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST
/**
* @}
*/
/** @defgroup SPI_TI_Mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLE (0x00000000U)
#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0
/**
* @}
*/
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN
/**
* @}
*/
/** @defgroup SPI_CRC_length SPI CRC Length
* @{
*/
#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define SPI_CRC_LENGTH_4BIT (0x00030000U)
#define SPI_CRC_LENGTH_5BIT (0x00040000U)
#define SPI_CRC_LENGTH_6BIT (0x00050000U)
#define SPI_CRC_LENGTH_7BIT (0x00060000U)
#define SPI_CRC_LENGTH_8BIT (0x00070000U)
#define SPI_CRC_LENGTH_9BIT (0x00080000U)
#define SPI_CRC_LENGTH_10BIT (0x00090000U)
#define SPI_CRC_LENGTH_11BIT (0x000A0000U)
#define SPI_CRC_LENGTH_12BIT (0x000B0000U)
#define SPI_CRC_LENGTH_13BIT (0x000C0000U)
#define SPI_CRC_LENGTH_14BIT (0x000D0000U)
#define SPI_CRC_LENGTH_15BIT (0x000E0000U)
#define SPI_CRC_LENGTH_16BIT (0x000F0000U)
#define SPI_CRC_LENGTH_17BIT (0x00100000U)
#define SPI_CRC_LENGTH_18BIT (0x00110000U)
#define SPI_CRC_LENGTH_19BIT (0x00120000U)
#define SPI_CRC_LENGTH_20BIT (0x00130000U)
#define SPI_CRC_LENGTH_21BIT (0x00140000U)
#define SPI_CRC_LENGTH_22BIT (0x00150000U)
#define SPI_CRC_LENGTH_23BIT (0x00160000U)
#define SPI_CRC_LENGTH_24BIT (0x00170000U)
#define SPI_CRC_LENGTH_25BIT (0x00180000U)
#define SPI_CRC_LENGTH_26BIT (0x00190000U)
#define SPI_CRC_LENGTH_27BIT (0x001A0000U)
#define SPI_CRC_LENGTH_28BIT (0x001B0000U)
#define SPI_CRC_LENGTH_29BIT (0x001C0000U)
#define SPI_CRC_LENGTH_30BIT (0x001D0000U)
#define SPI_CRC_LENGTH_31BIT (0x001E0000U)
#define SPI_CRC_LENGTH_32BIT (0x001F0000U)
/**
* @}
*/
/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold
* @{
*/
#define SPI_FIFO_THRESHOLD_01DATA (0x00000000U)
#define SPI_FIFO_THRESHOLD_02DATA (0x00000020U)
#define SPI_FIFO_THRESHOLD_03DATA (0x00000040U)
#define SPI_FIFO_THRESHOLD_04DATA (0x00000060U)
#define SPI_FIFO_THRESHOLD_05DATA (0x00000080U)
#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0U)
#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0U)
#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0U)
#define SPI_FIFO_THRESHOLD_09DATA (0x00000100U)
#define SPI_FIFO_THRESHOLD_10DATA (0x00000120U)
#define SPI_FIFO_THRESHOLD_11DATA (0x00000140U)
#define SPI_FIFO_THRESHOLD_12DATA (0x00000160U)
#define SPI_FIFO_THRESHOLD_13DATA (0x00000180U)
#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0U)
#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0U)
#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0U)
/**
* @}
*/
/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern
* @{
*/
#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000U)
#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001U)
/**
* @}
*/
/** @defgroup SPI_NSS_Polarity SPI NSS Polarity
* @{
*/
#define SPI_NSS_POLARITY_LOW (0x00000000U)
#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP
/**
* @}
*/
/** @defgroup SPI_Master_Keep_IO_State Keep IO State
* @{
*/
#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)
#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR
/**
* @}
*/
/** @defgroup SPI_IO_Swap Control SPI IO Swap
* @{
*/
#define SPI_IO_SWAP_DISABLE (0x00000000U)
#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP
/**
* @}
*/
/** @defgroup SPI_Master_SS_Idleness SPI Master SS Ideleness
* @{
*/
#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000U)
#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001U)
#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002U)
#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003U)
#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004U)
#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005U)
#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006U)
#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007U)
#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008U)
#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009U)
#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AU)
#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BU)
#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CU)
#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DU)
#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EU)
#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FU)
/**
* @}
*/
/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Ideleness
* @{
*/
#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000U)
#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010U)
#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020U)
#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030U)
#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040U)
#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050U)
#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060U)
#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070U)
#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080U)
#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090U)
#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0U)
#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0U)
#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0U)
#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0U)
#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0U)
#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0U)
/**
* @}
*/
/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend
* @{
*/
#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000U)
#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX
/**
* @}
*/
/** @defgroup SPI_Underrun_Detection SPI Underrun Detection
* @{
*/
#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000U)
#define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0
#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1
/**
* @}
*/
/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behaviour
* @{
*/
#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000U)
#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0
#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1
/**
* @}
*/
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_IER_TXPIE
#define SPI_IT_RXNE SPI_IER_RXPIE
#define SPI_IT_EOT SPI_IER_EOTIE
#define SPI_IT_TXTF SPI_IER_TXTFIE
#define SPI_IT_UDR SPI_IER_UDRIE
#define SPI_IT_OVR SPI_IER_OVRIE
#define SPI_IT_FRE SPI_IER_TIFREIE
#define SPI_IT_MODF SPI_IER_MODFIE
#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)
/**
* @}
*/
/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
#define SPI_FLAG_TXE SPI_SR_TXP /* SPI status flag: Tx buffer empty flag */
#define SPI_FLAG_RXNE SPI_SR_RXP /* SPI status flag: Rx buffer not empty flag */
#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag: Underrun flag */
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag: TI mode frame format error flag */
#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag: CRC error flag */
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI fifo reception level */
#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI RxFIFO Word Not Empty */
#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI Transmission Transfer Filled flag */
#define SPI_FLAG_EOT SPI_SR_EOT /* SPI fifo transmision complete */
#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI transfer suspend complete */
/**
* @}
*/
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
*/
#define SPI_FRLVL_EMPTY (0x00000000U)
#define SPI_FRLVL_QUARTER_FULL (0x00002000U)
#define SPI_FRLVL_HALF_FULL (0x00004000U)
#define SPI_FRLVL_FULL (0x00006000U)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
/** @brief Reset SPI handle state.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disable the specified SPI interrupts.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param __INTERRUPT__: specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param __INTERRUPT__: specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_TXE : Tx buffer empty flag
* @arg SPI_FLAG_RXNE : Rx buffer not empty flag
* @arg SPI_FLAG_UDR : Underrun flag
* @arg SPI_FLAG_OVR : Overrun flag
* @arg SPI_FLAG_FRE : TI mode frame format error flag
* @arg SPI_FLAG_CRCERR: CRC error flag
* @arg SPI_FLAG_MODF : Mode fault flag
* @arg SPI_FLAG_FRLVL : fifo reception level
* @arg SPI_FLAG_RXWNE : RxFIFO Word Not Empty
* @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag
* @arg SPI_FLAG_EOT : fifo transmision complete
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the SPI CRCERR pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)
/** @brief Clear the SPI MODF pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)
/** @brief Clear the SPI UDR pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)
/** @brief Clear the SPI EOT pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)
/** @brief Clear the SPI UDR pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)
/** @brief Clear the SPI SUSP pending flag.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
/** @brief Disable the SPI peripheral.
* @param __HANDLE__: specifies the SPI Handle.
* @retval None
*/
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)
/**
* @}
*/
/* Include SPI HAL Extension module */
#include "stm32h7xx_hal_spi_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA (SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
/** @brief Set the SPI transmit-only mode.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)
/** @brief Set the SPI receive-only mode.
* @param __HANDLE__: specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)
#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
((MODE) == SPI_MODE_MASTER))
#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
((MODE) == SPI_DIRECTION_1LINE) || \
((MODE) == SPI_DIRECTION_2LINES_TXONLY))
#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) ( \
((MODE) == SPI_DIRECTION_2LINES)|| \
((MODE) == SPI_DIRECTION_1LINE) || \
((MODE) == SPI_DIRECTION_2LINES_TXONLY))
#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) ( \
((MODE) == SPI_DIRECTION_2LINES)|| \
((MODE) == SPI_DIRECTION_1LINE) || \
((MODE) == SPI_DIRECTION_2LINES_RXONLY))
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \
((DATASIZE) == SPI_DATASIZE_31BIT) || \
((DATASIZE) == SPI_DATASIZE_30BIT) || \
((DATASIZE) == SPI_DATASIZE_29BIT) || \
((DATASIZE) == SPI_DATASIZE_28BIT) || \
((DATASIZE) == SPI_DATASIZE_27BIT) || \
((DATASIZE) == SPI_DATASIZE_26BIT) || \
((DATASIZE) == SPI_DATASIZE_25BIT) || \
((DATASIZE) == SPI_DATASIZE_24BIT) || \
((DATASIZE) == SPI_DATASIZE_23BIT) || \
((DATASIZE) == SPI_DATASIZE_22BIT) || \
((DATASIZE) == SPI_DATASIZE_21BIT) || \
((DATASIZE) == SPI_DATASIZE_20BIT) || \
((DATASIZE) == SPI_DATASIZE_22BIT) || \
((DATASIZE) == SPI_DATASIZE_19BIT) || \
((DATASIZE) == SPI_DATASIZE_18BIT) || \
((DATASIZE) == SPI_DATASIZE_17BIT) || \
((DATASIZE) == SPI_DATASIZE_16BIT) || \
((DATASIZE) == SPI_DATASIZE_15BIT) || \
((DATASIZE) == SPI_DATASIZE_14BIT) || \
((DATASIZE) == SPI_DATASIZE_13BIT) || \
((DATASIZE) == SPI_DATASIZE_12BIT) || \
((DATASIZE) == SPI_DATASIZE_11BIT) || \
((DATASIZE) == SPI_DATASIZE_10BIT) || \
((DATASIZE) == SPI_DATASIZE_9BIT) || \
((DATASIZE) == SPI_DATASIZE_8BIT) || \
((DATASIZE) == SPI_DATASIZE_7BIT) || \
((DATASIZE) == SPI_DATASIZE_6BIT) || \
((DATASIZE) == SPI_DATASIZE_5BIT) || \
((DATASIZE) == SPI_DATASIZE_4BIT))
#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \
((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
((CPOL) == SPI_POLARITY_HIGH))
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
((CPHA) == SPI_PHASE_2EDGE))
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
((NSS) == SPI_NSS_HARD_INPUT) || \
((NSS) == SPI_NSS_HARD_OUTPUT))
#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
((NSSP) == SPI_NSS_PULSE_DISABLE))
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
((BIT) == SPI_FIRSTBIT_LSB))
#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
((MODE) == SPI_TIMODE_ENABLE))
#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \
((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))
#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
((LENGTH) == SPI_CRC_LENGTH_32BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_31BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_30BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_29BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_28BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_27BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_26BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_25BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_24BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_23BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_22BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_21BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_20BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_19BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_18BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_17BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_16BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_15BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_14BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_13BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_12BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_11BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_10BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_9BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_8BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_7BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_6BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_5BIT) ||\
((LENGTH) == SPI_CRC_LENGTH_4BIT))
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
#define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \
((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))
#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \
((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \
((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SPI_H */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_spi_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SPI HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SPI_EX_H
#define __STM32H7xx_HAL_SPI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SPIEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPIEx_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/* IO operation functions *****************************************************/
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SPI_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h
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/**
******************************************************************************
* @file stm32h7xx_hal_sram.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SRAM_H
#define __STM32H7xx_HAL_SRAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_ll_fmc.h"
#include "stm32h7xx_hal_mdma.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SRAM
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SRAM_Exported_Types SRAM Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
}HAL_SRAM_StateTypeDef;
/**
* @brief SRAM handle Structure definition
*/
typedef struct
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
HAL_LockTypeDef Lock; /*!< SRAM locking object */
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
MDMA_HandleTypeDef *hmdma; /*!< Pointer DMA handler */
}SRAM_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
* @{
*/
/** @brief Reset SRAM handle state
* @param __HANDLE__: SRAM handle
* @retval None
*/
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);
void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
* @{
*/
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SRAM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_swpmi.h
+467
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/**
******************************************************************************
* @file stm32h7xx_hal_swpmi.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of SWPMI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_SWPMI_H
#define __STM32H7xx_HAL_SWPMI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup SWPMI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SWPMI_Exported_Types SWPMI Exported Types
* @{
*/
/**
* @brief SWPMI Init Structure definition
*/
typedef struct
{
uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class.
This parameter can be a value of @ref SWPMI_Voltage_Class */
uint32_t BitRate; /*!< Specifies the SWPMI Bitrate.
This parameter must be a number between 0 and 63.
The Bitrate is computed using the following formula:
SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4)
*/
uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode.
This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */
uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode.
This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */
}SWPMI_InitTypeDef;
/**
* @brief HAL SWPMI State structures definition
*/
typedef enum
{
HAL_SWPMI_STATE_RESET = 0x00, /*!< Peripheral Reset state */
HAL_SWPMI_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_SWPMI_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_SWPMI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_SWPMI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_SWPMI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_SWPMI_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_SWPMI_STATE_ERROR = 0x04 /*!< Error */
}HAL_SWPMI_StateTypeDef;
/**
* @brief SWPMI handle Structure definition
*/
typedef struct
{
SWPMI_TypeDef *Instance; /* SWPMI registers base address */
SWPMI_InitTypeDef Init; /* SWMPI communication parameters */
uint32_t *pTxBuffPtr; /* Pointer to SWPMI Tx transfer Buffer */
uint32_t TxXferSize; /* SWPMI Tx Transfer size */
uint32_t TxXferCount; /* SWPMI Tx Transfer Counter */
uint32_t *pRxBuffPtr; /* Pointer to SWPMI Rx transfer Buffer */
uint32_t RxXferSize; /* SWPMI Rx Transfer size */
uint32_t RxXferCount; /* SWPMI Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /* SWPMI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /* SWPMI Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /* SWPMI object */
__IO HAL_SWPMI_StateTypeDef State; /* SWPMI communication state */
__IO uint32_t ErrorCode; /* SWPMI Error code */
}SWPMI_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants
* @{
*/
/**
* @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap
* @{
*/
#define HAL_SWPMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_SWPMI_ERROR_CRC ((uint32_t)0x00000004) /*!< frame error */
#define HAL_SWPMI_ERROR_OVR ((uint32_t)0x00000008) /*!< Overrun error */
#define HAL_SWPMI_ERROR_UDR ((uint32_t)0x0000000C) /*!< Underrun error */
#define HAL_SWPMI_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
/**
* @}
*/
/** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class
* @{
*/
#define SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000)
#define SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS
/**
* @}
*/
/** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode
* @{
*/
#define SWPMI_TX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define SWPMI_TX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define SWPMI_TX_MULTI_SOFTWAREBUFFER SWPMI_CR_TXMODE
/**
* @}
*/
/** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode
* @{
*/
#define SWPMI_RX_NO_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define SWPMI_RX_SINGLE_SOFTWAREBUFFER ((uint32_t)0x00000000)
#define SWPMI_RX_MULTI_SOFTWAREBUFFER SWPMI_CR_RXMODE
/**
* @}
*/
/** @defgroup SWPMI_Flags SWPMI Status Flags
* Elements values convention: 0xXXXXXXXX
* - 0xXXXXXXXX : Flag mask in the ISR register
* @{
*/
#define SWPMI_FLAG_RXBFF SWPMI_ISR_RXBFF
#define SWPMI_FLAG_TXBEF SWPMI_ISR_TXBEF
#define SWPMI_FLAG_RXBERF SWPMI_ISR_RXBERF
#define SWPMI_FLAG_RXOVRF SWPMI_ISR_RXOVRF
#define SWPMI_FLAG_TXUNRF SWPMI_ISR_TXUNRF
#define SWPMI_FLAG_RXNE SWPMI_ISR_RXNE
#define SWPMI_FLAG_TXE SWPMI_ISR_TXE
#define SWPMI_FLAG_TCF SWPMI_ISR_TCF
#define SWPMI_FLAG_SRF SWPMI_ISR_SRF
#define SWPMI_FLAG_SUSP SWPMI_ISR_SUSP
#define SWPMI_FLAG_DEACTF SWPMI_ISR_DEACTF
#define SWPMI_FLAG_RDYF SWPMI_ISR_RDYF
/**
* @}
*/
/** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the IER register
* @{
*/
#define SWPMI_IT_RDYIE SWPMI_IER_RDYIE
#define SWPMI_IT_SRIE SWPMI_IER_SRIE
#define SWPMI_IT_TCIE SWPMI_IER_TCIE
#define SWPMI_IT_TIE SWPMI_IER_TIE
#define SWPMI_IT_RIE SWPMI_IER_RIE
#define SWPMI_IT_TXUNRIE SWPMI_IER_TXUNRIE
#define SWPMI_IT_RXOVRIE SWPMI_IER_RXOVRIE
#define SWPMI_IT_RXBERIE SWPMI_IER_RXBERIE
#define SWPMI_IT_TXBEIE SWPMI_IER_TXBEIE
#define SWPMI_IT_RXBFIE SWPMI_IER_RXBFIE
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros
* @{
*/
/** @brief Reset SWPMI handle state.
* @param __HANDLE__: specifies the SWPMI Handle.
* @retval None
*/
#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)
/**
* @brief Enable the SWPMI peripheral.
* @param __HANDLE__: SWPMI handle
* @retval None
*/
#define __HAL_SWPMI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
/**
* @brief Disable the SWPMI peripheral.
* @param __HANDLE__: SWPMI handle
* @retval None
*/
#define __HAL_SWPMI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)
/**
* @brief Enable/Disable the SWPMI transceiver.
* @param __HANDLE__: SWPMI handle
* @retval None
*/
#define __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
#define __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)
/** @brief Check whether the specified SWPMI flag is set or not.
* @param __HANDLE__: specifies the SWPMI Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
* @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
* @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
* @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
* @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
* @arg SWPMI_FLAG_RXNE : Receive data register not empty.
* @arg SWPMI_FLAG_TXE : Transmit data register empty.
* @arg SWPMI_FLAG_TCF : Transfer complete flag.
* @arg SWPMI_FLAG_SRF : Slave resume flag.
* @arg SWPMI_FLAG_SUSP : SUSPEND flag.
* @arg SWPMI_FLAG_DEACTF : DEACTIVATED flag.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified SWPMI ISR flag.
* @param __HANDLE__: specifies the SWPMI Handle.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg SWPMI_FLAG_RXBFF : Receive buffer full flag.
* @arg SWPMI_FLAG_TXBEF : Transmit buffer empty flag.
* @arg SWPMI_FLAG_RXBERF : Receive CRC error flag.
* @arg SWPMI_FLAG_RXOVRF : Receive overrun error flag.
* @arg SWPMI_FLAG_TXUNRF : Transmit underrun error flag.
* @arg SWPMI_FLAG_TCF : Transfer complete flag.
* @arg SWPMI_FLAG_SRF : Slave resume flag.
* @arg SWPMI_FLAG_RDYF: Transceiver ready flag
* @retval None
*/
#define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))
/** @brief Enable the specified SWPMI interrupt.
* @param __HANDLE__: specifies the SWPMI Handle.
* @param __INTERRUPT__: specifies the SWPMI interrupt source to enable.
* This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
* @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
* @retval None
*/
#define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
/** @brief Disable the specified SWPMI interrupt.
* @param __HANDLE__: specifies the SWPMI Handle.
* @param __INTERRUPT__: specifies the SWPMI interrupt source to disable.
* This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
* @arg SWPMI_IT_RXBEIE : Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
* @retval None
*/
#define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))
/** @brief Check whether the specified SWPMI interrupt has occurred or not.
* @param __HANDLE__: specifies the SWPMI Handle.
* @param __IT__: specifies the SWPMI interrupt to check.
* This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
* @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__) (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))
/** @brief Check whether the specified SWPMI interrupt source is enabled or not.
* @param __HANDLE__: specifies the SWPMI Handle.
* @param __IT__: specifies the SWPMI interrupt source to check.
* This parameter can be one of the following values:
* @arg SWPMI_IT_SRIE : Slave resume interrupt.
* @arg SWPMI_IT_TCIE : Transmit complete interrupt.
* @arg SWPMI_IT_TIE : Transmit interrupt.
* @arg SWPMI_IT_RIE : Receive interrupt.
* @arg SWPMI_IT_TXUNRIE : Transmit underrun error interrupt.
* @arg SWPMI_IT_RXOVRIE : Receive overrun error interrupt.
* @arg SWPMI_IT_RXBERIE : Receive CRC error interrupt.
* @arg SWPMI_IT_TXBEIE : Transmit buffer empty interrupt.
* @arg SWPMI_IT_RXBFIE : Receive buffer full interrupt.
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);
HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);
HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);
HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);
void HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);
/* Peripheral Control and State functions ************************************/
HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);
uint32_t HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup SWPMI_Private_Types SWPMI Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup SWPMI_Private_Variables SWPMI Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SWPMI_Private_Constants SWPMI Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SWPMI_Private_Macros SWPMI Private Macros
* @{
*/
#define IS_SWPMI_VOLTAGE_CLASS(__CLASS__) (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \
((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))
#define IS_SWPMI_BITRATE_VALUE(__VALUE__) (((__VALUE__) <= 63))
#define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \
((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))
#define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \
((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_SWPMI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h
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/**
******************************************************************************
* @file stm32h7xx_hal_tim_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_TIM_EX_H
#define __STM32H7xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
/**
* @brief TIM Break/Break2 input configuration
*/
typedef struct {
uint32_t Source; /*!< Specifies the source of the timer break input.
This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
Not relevant when analog watchdog output of the DFSDM1 used as break input source */
} TIMEx_BreakInputConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Channel TIM Extended Channel
* @{
*/
#define TIM_CHANNEL_1 ((uint32_t)0x0000U) /*!< TIM Channel 1*/
#define TIM_CHANNEL_2 ((uint32_t)0x0004U) /*!< TIM Channel 2*/
#define TIM_CHANNEL_3 ((uint32_t)0x0008U) /*!< TIM Channel 3*/
#define TIM_CHANNEL_4 ((uint32_t)0x000CU) /*!< TIM Channel 4*/
#define TIM_CHANNEL_5 ((uint32_t)0x0010U) /*!< TIM Channel 5*/
#define TIM_CHANNEL_6 ((uint32_t)0x0014U) /*!< TIM Channel 6*/
#define TIM_CHANNEL_ALL ((uint32_t)0x003CU) /*!< TIM all Channels */
/**
* @}
*/
/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
* @{
*/
#define TIM_OCMODE_TIMING ((uint32_t)0x0000U) /*!< TIM Output timing mode */
#define TIM_OCMODE_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_0) /*!< TIM Output Active mode */
#define TIM_OCMODE_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_1) /*!< TIM Output Inactive mode */
#define TIM_OCMODE_TOGGLE ((uint32_t)TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< TIM Output Toggle mode */
#define TIM_OCMODE_PWM1 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< TIM PWM mode 1 */
#define TIM_OCMODE_PWM2 ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< TIM PWM mode 2 */
#define TIM_OCMODE_FORCED_ACTIVE ((uint32_t)TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< TIM Forced Active mode */
#define TIM_OCMODE_FORCED_INACTIVE ((uint32_t)TIM_CCMR1_OC1M_2) /*!< TIM Forced Inactive mode */
#define TIM_OCMODE_RETRIGERRABLE_OPM1 ((uint32_t)TIM_CCMR1_OC1M_3) /*!< TIM Rettrigerrable OPM mode 1 */
#define TIM_OCMODE_RETRIGERRABLE_OPM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< TIM Rettrigerrable OPM mode 2 */
#define TIM_OCMODE_COMBINED_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< TIM Combined PWM mode 1 */
#define TIM_OCMODE_COMBINED_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< TIM Combined PWM mode 2 */
#define TIM_OCMODE_ASSYMETRIC_PWM1 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< TIM Asymetruc PWM mode 1 */
#define TIM_OCMODE_ASSYMETRIC_PWM2 ((uint32_t)TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!< TIM Asymetruc PWM mode 2 */
/**
* @}
*/
/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source
* @{
*/
#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) /*!< TIM Clear input source connected to ETR */
#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002U) /*!< TIM Clear input source connected to OCREFClear */
#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) /*!< TIM Clear input source None */
/**
* @}
*/
/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable
* @{
*/
#define TIM_BREAK2_DISABLE ((uint32_t)0x00000000U) /*!< TIM Break2 disabled */
#define TIM_BREAK2_ENABLE ((uint32_t)TIM_BDTR_BK2E) /*!< TIM Break2 enabled */
/**
* @}
*/
/** @defgroup TIMEx_Break2_Polarity TIM Extended Break Input 2 Polarity
* @{
*/
#define TIM_BREAK2POLARITY_LOW ((uint32_t)0x00000000U) /*!< TIM Break2 polarity low */
#define TIM_BREAK2POLARITY_HIGH ((uint32_t)TIM_BDTR_BK2P) /*!< TIM Break2 polarity high */
/**
* @}
*/
/** @defgroup TIMEx_Trigger_Selection TIM Trigger Selection
* @{
*/
#define TIM_TS_ITR4 ((uint32_t)0x0100000) /*!< TIM Internal trigger 4 */
#define TIM_TS_ITR5 ((uint32_t)0x0100010) /*!< TIM Internal trigger 5 */
#define TIM_TS_ITR6 ((uint32_t)0x0100020) /*!< TIM Internal trigger 6 */
#define TIM_TS_ITR7 ((uint32_t)0x0100030) /*!< TIM Internal trigger 7 */
#define TIM_TS_ITR8 ((uint32_t)0x0100040) /*!< TIM Internal trigger 8 */
/**
* @}
*/
/** @defgroup TIM_Event_Source TIM Extended Event Source
* @{
*/
#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
/**
* @}
*/
/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
* @{
*/
#define TIM_DMABASE_CR1 (0x00000000U) /*!< TIM DMA Base Address is CR1 */
#define TIM_DMABASE_CR2 (0x00000001U) /*!< TIM DMA Base Address is CR2 */
#define TIM_DMABASE_SMCR (0x00000002U) /*!< TIM DMA Base Address is SMCR */
#define TIM_DMABASE_DIER (0x00000003U) /*!< TIM DMA Base Address is DIER */
#define TIM_DMABASE_SR (0x00000004U) /*!< TIM DMA Base Address is SR */
#define TIM_DMABASE_EGR (0x00000005U) /*!< TIM DMA Base Address is EGR */
#define TIM_DMABASE_CCMR1 (0x00000006U) /*!< TIM DMA Base Address is CCMR1 */
#define TIM_DMABASE_CCMR2 (0x00000007U) /*!< TIM DMA Base Address is CCMR2*/
#define TIM_DMABASE_CCER (0x00000008U) /*!< TIM DMA Base Address is CCER */
#define TIM_DMABASE_CNT (0x00000009U) /*!< TIM DMA Base Address is CNT */
#define TIM_DMABASE_PSC (0x0000000AU) /*!< TIM DMA Base Address is PSC */
#define TIM_DMABASE_ARR (0x0000000BU) /*!< TIM DMA Base Address is ARR */
#define TIM_DMABASE_RCR (0x0000000CU) /*!< TIM DMA Base Address is RCR */
#define TIM_DMABASE_CCR1 (0x0000000DU) /*!< TIM DMA Base Address is CCR1 */
#define TIM_DMABASE_CCR2 (0x0000000EU) /*!< TIM DMA Base Address is CCR2 */
#define TIM_DMABASE_CCR3 (0x0000000FU) /*!< TIM DMA Base Address is CCR3 */
#define TIM_DMABASE_CCR4 (0x00000010U) /*!< TIM DMA Base Address is CCR3 */
#define TIM_DMABASE_BDTR (0x00000011U) /*!< TIM DMA Base Address is BDTR */
#define TIM_DMABASE_DCR (0x00000012U) /*!< TIM DMA Base Address is DCR */
#define TIM_DMABASE_DMAR (0x00000013U) /*!< TIM DMA Base Address is DMAR */
#define TIM_DMABASE_AF1 (0x00000014U) /*!< TIM DMA Base Address is AF1 */
#define TIM_DMABASE_CCMR3 (0x00000015U) /*!< TIM DMA Base Address is CCMR3 */
#define TIM_DMABASE_CCR5 (0x00000016U) /*!< TIM DMA Base Address is CCR5 */
#define TIM_DMABASE_CCR6 (0x00000017U) /*!< TIM DMA Base Address is CCR6 */
#define TIM_DMABASE_AF2 (0x00000018U) /*!< TIM DMA Base Address is AF2 */
#define TIM_DMABASE_AF3 (0x00000019U) /*!< TIM DMA Base Address is AF3 */
#define TIM_DMABASE_TISEL (0x0000001AU) /*!< TIM DMA Base Address is TISEL */
/**
* @}
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#define TIM_TIM1_ETR_GPIO (0x00000000) /* !< TIM1_ETR is connected to GPIO */
#define TIM_TIM1_ETR_ADC1_AWD1 (0x0000C000) /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 (0x00010000) /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (0x00014000) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#define TIM_TIM1_ETR_ADC3_AWD1 (0x00018000) /* !< TIM1_ETR is connected to ADC3 AWD1 */
#define TIM_TIM1_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM1_ETR is connected to ADC3 AWD2 */
#define TIM_TIM1_ETR_ADC3_AWD3 (0x00020000) /* !< TIM1_ETR is connected to ADC3 AWD3 */
#define TIM_TIM1_ETR_COMP1_OUT (0x00004000) /* !< TIM1_ETR is connected to COMP1 OUT */
#define TIM_TIM1_ETR_COMP2_OUT (0x00008000) /* !< TIM1_ETR is connected to COMP2 OUT */
#define TIM_TIM8_ETR_GPIO (0x00000000) /* !< TIM8_ETR is connected to GPIO */
#define TIM_TIM8_ETR_ADC2_AWD1 (0x0000C000) /* !< TIM8_ETR is connected to ADC2 AWD1 */
#define TIM_TIM8_ETR_ADC2_AWD2 (0x00010000) /* !< TIM8_ETR is connected to ADC2 AWD2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (0x00014000) /* !< TIM8_ETR is connected to ADC2 AWD3 */
#define TIM_TIM8_ETR_ADC3_AWD1 (0x00018000) /* !< TIM8_ETR is connected to ADC3 AWD1 */
#define TIM_TIM8_ETR_ADC3_AWD2 (0x0001C000) /* !< TIM8_ETR is connected to ADC3 AWD2 */
#define TIM_TIM8_ETR_ADC3_AWD3 (0x00020000) /* !< TIM8_ETR is connected to ADC3 AWD3 */
#define TIM_TIM8_ETR_COMP1_OUT (0x00004000) /* !< TIM8_ETR is connected to COMP1 OUT */
#define TIM_TIM8_ETR_COMP2_OUT (0x00008000) /* !< TIM8_ETR is connected to COMP2 OUT */
#define TIM_TIM2_ETR_GPIO (0x00000000) /* !< TIM2_ETR is connected to GPIO */
#define TIM_TIM2_ETR_COMP1_OUT (0x0000C000) /* !< TIM2_ETR is connected to COMP1 OUT */
#define TIM_TIM2_ETR_COMP2_OUT (0x00010000) /* !< TIM2_ETR is connected to COMP2 OUT */
#define TIM_TIM2_ETR_RCC_LSE (0x00014000) /* !< TIM2_ETR is connected to RCC LSE */
#define TIM_TIM2_ETR_SAI1_FSA (0x00018000) /* !< TIM2_ETR is connected to SAI1 FS_A */
#define TIM_TIM2_ETR_SAI1_FSB (0x0001C000) /* !< TIM2_ETR is connected to SAI1 FS_B */
#define TIM_TIM3_ETR_GPIO (0x00000000) /* !< TIM3_ETR is connected to GPIO */
#define TIM_TIM3_ETR_COMP1_OUT (0x00000000) /* !< TIM3_ETR is connected to COMP1 OUT */
#define TIM_TIM5_ETR_GPIO (0x00000000) /* !< TIM5_ETR is connected to GPIO */
#define TIM_TIM5_ETR_SAI2_FSA (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_A */
#define TIM_TIM5_ETR_SAI2_FSB (0x00000000) /* !< TIM5_ETR is connected to SAI2 FS_B */
#define TIM_TIM1_BKR_GPIO (0x00000000) /* !< TIM1_BKR is connected to GPIO */
#define TIM_TIM1_BKR_COMP1_OUT (0x00000002) /* !< TIM1_BKR is connected to COMP1 OUT */
#define TIM_TIM1_BKR_COMP2_OUT (0x00000004) /* !< TIM1_BKR is connected to COMP2 OUT */
#define TIM_TIM1_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM1_BKR is connected to DFSDM BRK0 */
#define TIM_TIM8_BKR_GPIO (0x00000000) /* !< TIM8_BKR is connected to GPIO */
#define TIM_TIM8_BKR_COMP1_OUT (0x00000002) /* !< TIM8_BKR is connected to COMP1 OUT */
#define TIM_TIM8_BKR_COMP2_OUT (0x00000004) /* !< TIM8_BKR is connected to COMP2 OUT */
#define TIM_TIM8_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM8_BKR is connected to DFSDM BRK2 */
#define TIM_TIM15_BKR_GPIO (0x00000000) /* !< TIM15_BKR is connected to GPIO */
#define TIM_TIM15_BKR_COMP1_OUT (0x00000002) /* !< TIM15_BKR is connected to COMP1 OUT */
#define TIM_TIM15_BKR_COMP2_OUT (0x00000004) /* !< TIM15_BKR is connected to COMP2 OUT */
#define TIM_TIM15_BKR_DFSDM_BRK0 (0x00000000) /* !< TIM15_BKR is connected to DFSDM BRK0 */
#define TIM_TIM16_BKR_GPIO (0x00000000) /* !< TIM16_BKR is connected to GPIO */
#define TIM_TIM16_BKR_COMP1_OUT (0x00000002) /* !< TIM16_BKR is connected to COMP1 OUT */
#define TIM_TIM16_BKR_COMP2_OUT (0x00000004) /* !< TIM16_BKR is connected to COMP2 OUT */
#define TIM_TIM16_BKR_DFSDM_BRK1 (0x00000000) /* !< TIM16_BKR is connected to DFSDM BRK1 */
#define TIM_TIM17_BKR_GPIO (0x00000000) /* !< TIM17_BKR is connected to GPIO */
#define TIM_TIM17_BKR_COMP1_OUT (0x00000002) /* !< TIM17_BKR is connected to COMP1 OUT */
#define TIM_TIM17_BKR_COMP2_OUT (0x00000004) /* !< TIM17_BKR is connected to COMP2 OUT */
#define TIM_TIM17_BKR_DFSDM_BRK2 (0x00000000) /* !< TIM17_BKR is connected to DFSDM BRK2 */
#define TIM_TIM1_BKR2_GPIO (0x00000000) /* !< TIM1_BKR2 is connected to GPIO */
#define TIM_TIM1_BKR2_COMP1_OUT (0x00000002) /* !< TIM1_BKR2 is connected to COMP1 OUT */
#define TIM_TIM1_BKR2_COMP2_OUT (0x00000004) /* !< TIM1_BKR2 is connected to COMP2 OUT */
#define TIM_TIM1_BKR2_DFSDM_BRK1 (0x00000000) /* !< TIM1_BKR2 is connected to DFSDM BRK0 */
#define TIM_TIM8_BKR2_GPIO (0x00000000) /* !< TIM8_BKR2 is connected to GPIO */
#define TIM_TIM8_BKR2_COMP1_OUT (0x00000002) /* !< TIM8_BKR2 is connected to COMP1 OUT */
#define TIM_TIM8_BKR2_COMP2_OUT (0x00000004) /* !< TIM8_BKR2 is connected to COMP2 OUT */
#define TIM_TIM8_BKR2_DFSDM_BRK3 (0x00000000) /* !< TIM8_BKR2 is connected to DFSDM BRK3 */
#define TIM_TIM1_TI1_GPIO (0x00000000) /* !< TIM1_TI1 is connected to GPIO */
#define TIM_TIM1_TI1_COMP1_OUT (0x00000001) /* !< TIM1_TI1 is connected to COMP1 OUT */
#define TIM_TIM8_TI1_GPIO (0x00000000) /* !< TIM8_TI1 is connected to GPIO */
#define TIM_TIM8_TI1_COMP2_OUT (0x00000001) /* !< TIM8_TI1 is connected to COMP2 OUT */
#define TIM_TIM2_TI4_GPIO (0x00000000) /* !< TIM2_TI4 is connected to GPIO */
#define TIM_TIM2_TI4_COMP1_OUT (0x01000000) /* !< TIM2_TI4 is connected to COMP1 OUT */
#define TIM_TIM2_TI4_COMP2_OUT (0x02000000) /* !< TIM2_TI4 is connected to COMP2 OUT */
#define TIM_TIM2_TI4_COMP1COMP2_OUT (0x03000000) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */
#define TIM_TIM3_TI1_GPIO (0x00000000) /* !< TIM3_TI1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1_OUT (0x00000001) /* !< TIM3_TI1 is connected to COMP1 OUT */
#define TIM_TIM3_TI1_COMP2_OUT (0x00000002) /* !< TIM3_TI1 is connected to COMP2 OUT */
#define TIM_TIM3_TI1_COMP1COMP2_OUT (0x00000003) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
#define TIM_TIM5_TI1_GPIO (0x00000000) /* !< TIM5_TI1 is connected to GPIO */
#define TIM_TIM5_TI1_CAN_TMP (0x00000001) /* !< TIM5_TI1 is connected to CAN TMP */
#define TIM_TIM5_TI1_CAN_RTP (0x00000002) /* !< TIM5_TI1 is connected to CAN RTP */
#define TIM_TIM15_TI1_GPIO (0x00000000) /* !< TIM15_TI1 is connected to GPIO */
#define TIM_TIM15_TI1_TIM2_CH1 (0x00000001) /* !< TIM15_TI1 is connected to TIM2 CH1 */
#define TIM_TIM15_TI1_TIM3_CH1 (0x00000002) /* !< TIM15_TI1 is connected to TIM3 CH1 */
#define TIM_TIM15_TI1_TIM4_CH1 (0x00000003) /* !< TIM15_TI1 is connected to TIM4 CH1 */
#define TIM_TIM15_TI1_RCC_LSE (0x00000004) /* !< TIM15_TI1 is connected to RCC LSE */
#define TIM_TIM15_TI1_RCC_CSI (0x00000005) /* !< TIM15_TI1 is connected to RCC CSI */
#define TIM_TIM15_TI1_RCC_MCO2 (0x00000006) /* !< TIM15_TI1 is connected to RCC MCO2 */
#define TIM_TIM15_TI2_GPIO (0x00000000) /* !< TIM15_TI2 is connected to GPIO */
#define TIM_TIM15_TI2_TIM2_CH2 (0x00000100) /* !< TIM15_TI2 is connected to TIM2 CH2 */
#define TIM_TIM15_TI2_TIM3_CH2 (0x00000200) /* !< TIM15_TI2 is connected to TIM3 CH2 */
#define TIM_TIM15_TI2_TIM4_CH2 (0x00000300) /* !< TIM15_TI2 is connected to TIM4 CH2 */
#define TIM_TIM16_TI1_GPIO (0x00000000) /* !< TIM16 TI1 is connected to GPIO */
#define TIM_TIM16_TI1_RCC_LSI (0x00000001) /* !< TIM16 TI1 is connected to RCC LSI */
#define TIM_TIM16_TI1_RCC_LSE (0x00000002) /* !< TIM16 TI1 is connected to RCC LSE */
#define TIM_TIM16_TI1_WKUP_IT (0x00000003) /* !< TIM16 TI1 is connected to WKUP_IT */
#define TIM_TIM17_TI1_GPIO (0x00000000) /* !< TIM17 TI1 is connected to GPIO */
#define TIM_TIM17_TI1_SPDIF_FS (0x00000001) /* !< TIM17 TI1 is connected to RCC LSI */
#define TIM_TIM17_TI1_RCC_HSE1MHZ (0x00000002) /* !< TIM17 TI1 is connected to RCC LSE */
#define TIM_TIM17_TI1_RCC_MCO1 (0x00000003) /* !< TIM17 TI1 is connected to RCC MCO1 */
/**
* @}
*/
/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3
* @{
*/
#define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define TIM_GROUPCH5_OC1REFC (TIM_CCR5_GC5C1) /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define TIM_GROUPCH5_OC2REFC (TIM_CCR5_GC5C2) /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define TIM_GROUPCH5_OC3REFC (TIM_CCR5_GC5C3) /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
#define TIM_BREAKINPUT_BRK ((uint32_t)(0x00000001)) /* !< Timer break input */
#define TIM_BREAKINPUT_BRK2 ((uint32_t)(0x00000002)) /* !< Timer break2 input */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin */
#define TIM_BREAKINPUTSOURCE_COMP1 ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP2 ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
#define TIM_BREAKINPUTSOURCE_DISABLE ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
#define TIM_BREAKINPUTSOURCE_ENABLE ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#define IS_TIM_REMAP(__REMAP__) (((__REMAP__) <= (uint32_t)0x0001C01F))
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
#define IS_TIM_TISEL(TISEL) (((TISEL) == TIM_TIM1_TI1_GPIO) ||\
((TISEL) == TIM_TIM1_TI1_COMP1_OUT) ||\
((TISEL) == TIM_TIM8_TI1_GPIO) ||\
((TISEL) == TIM_TIM8_TI1_COMP2_OUT) ||\
((TISEL) == TIM_TIM2_TI4_GPIO) ||\
((TISEL) == TIM_TIM2_TI4_COMP1_OUT) ||\
((TISEL) == TIM_TIM2_TI4_COMP2_OUT) ||\
((TISEL) == TIM_TIM2_TI4_COMP1COMP2_OUT) ||\
((TISEL) == TIM_TIM3_TI1_GPIO) ||\
((TISEL) == TIM_TIM3_TI1_COMP1_OUT) ||\
((TISEL) == TIM_TIM3_TI1_COMP2_OUT) ||\
((TISEL) == TIM_TIM3_TI1_COMP1COMP2_OUT) ||\
((TISEL) == TIM_TIM5_TI1_GPIO) ||\
((TISEL) == TIM_TIM5_TI1_CAN_TMP) ||\
((TISEL) == TIM_TIM5_TI1_CAN_RTP) ||\
((TISEL) == TIM_TIM15_TI1_GPIO) ||\
((TISEL) == TIM_TIM15_TI1_TIM2_CH1) ||\
((TISEL) == TIM_TIM15_TI1_TIM3_CH1) ||\
((TISEL) == TIM_TIM15_TI1_TIM4_CH1) ||\
((TISEL) == TIM_TIM15_TI1_RCC_LSE) ||\
((TISEL) == TIM_TIM15_TI1_RCC_CSI) ||\
((TISEL) == TIM_TIM15_TI1_RCC_MCO2) ||\
((TISEL) == TIM_TIM15_TI2_GPIO) ||\
((TISEL) == TIM_TIM15_TI2_TIM2_CH2) ||\
((TISEL) == TIM_TIM15_TI2_TIM3_CH2) ||\
((TISEL) == TIM_TIM15_TI2_TIM4_CH2) ||\
((TISEL) == TIM_TIM16_TI1_GPIO) ||\
((TISEL) == TIM_TIM16_TI1_RCC_LSI) ||\
((TISEL) == TIM_TIM16_TI1_RCC_LSE) ||\
((TISEL) == TIM_TIM16_TI1_WKUP_IT) ||\
((TISEL) == TIM_TIM17_TI1_GPIO) ||\
((TISEL) == TIM_TIM17_TI1_SPDIF_FS) ||\
((TISEL) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
((TISEL) == TIM_TIM17_TI1_RCC_MCO1))
#define IS_TIM_BKR2REMAP(BK2RREMAP) (((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKR2REMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKR2REMAP) == TIM_TIM1_BKR_GPIO))
#define IS_TIM_BKRREMAP(BKRREMAP) (((BKRREMAP) == TIM_TIM1_BKR_GPIO) ||\
((BKRREMAP) == TIM_TIM1_BKR_COMP1_OUT) ||\
((BKRREMAP) == TIM_TIM1_BKR_COMP2_OUT) ||\
((BKRREMAP) == TIM_TIM1_BKR_DFSDM_BRK0) ||\
((BKRREMAP) == TIM_TIM8_BKR_GPIO) ||\
((BKRREMAP) == TIM_TIM8_BKR_COMP1_OUT) ||\
((BKRREMAP) == TIM_TIM8_BKR_COMP2_OUT) ||\
((BKRREMAP) == TIM_TIM8_BKR_DFSDM_BRK2) ||\
((BKRREMAP) == TIM_TIM15_BKR_GPIO) ||\
((BKRREMAP) == TIM_TIM15_BKR_COMP1_OUT) ||\
((BKRREMAP) == TIM_TIM15_BKR_COMP2_OUT) ||\
((BKRREMAP) == TIM_TIM15_BKR_DFSDM_BRK0) ||\
((BKRREMAP) == TIM_TIM16_BKR_GPIO) ||\
((BKRREMAP) == TIM_TIM16_BKR_COMP1_OUT) ||\
((BKRREMAP) == TIM_TIM16_BKR_COMP2_OUT) ||\
((BKRREMAP) == TIM_TIM16_BKR_DFSDM_BRK1) ||\
((BKRREMAP) == TIM_TIM17_BKR_GPIO) ||\
((BKRREMAP) == TIM_TIM17_BKR_COMP1_OUT) ||\
((BKRREMAP) == TIM_TIM17_BKR_COMP2_OUT) ||\
((BKRREMAP) == TIM_TIM17_BKR_DFSDM_BRK2))
#define IS_TIM_ETRREMAP(ETRREMAP) (((ETRREMAP) == TIM_TIM1_ETR_GPIO) ||\
((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD1) ||\
((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD2) ||\
((ETRREMAP) == TIM_TIM1_ETR_ADC1_AWD3) ||\
((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD1) ||\
((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD2) ||\
((ETRREMAP) == TIM_TIM1_ETR_ADC3_AWD3) ||\
((ETRREMAP) == TIM_TIM1_ETR_COMP1_OUT) ||\
((ETRREMAP) == TIM_TIM1_ETR_COMP2_OUT) ||\
((ETRREMAP) == TIM_TIM8_ETR_GPIO) ||\
((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD1) ||\
((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD2) ||\
((ETRREMAP) == TIM_TIM8_ETR_ADC2_AWD3) ||\
((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD1) ||\
((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD2) ||\
((ETRREMAP) == TIM_TIM8_ETR_ADC3_AWD3) ||\
((ETRREMAP) == TIM_TIM8_ETR_COMP1_OUT) ||\
((ETRREMAP) == TIM_TIM8_ETR_COMP2_OUT) ||\
((ETRREMAP) == TIM_TIM2_ETR_GPIO) ||\
((ETRREMAP) == TIM_TIM2_ETR_COMP1_OUT) ||\
((ETRREMAP) == TIM_TIM2_ETR_COMP2_OUT) ||\
((ETRREMAP) == TIM_TIM2_ETR_RCC_LSE) ||\
((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSA) ||\
((ETRREMAP) == TIM_TIM2_ETR_SAI1_FSB) ||\
((ETRREMAP) == TIM_TIM3_ETR_GPIO) ||\
((ETRREMAP) == TIM_TIM3_ETR_COMP1_OUT) ||\
((ETRREMAP) == TIM_TIM5_ETR_GPIO) ||\
((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSA) |\
((ETRREMAP) == TIM_TIM5_ETR_SAI2_FSB))
/**
* @}
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection , uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions
* @{
*/
/* Extended Callback *********************************************************/
void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
* @brief Extended Peripheral State functions
* @{
*/
/* Extended Peripheral State functions **************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/**
* @}
*/
/* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{
*/
void HAL_TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_TIM_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h
+1633
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h
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@@ -0,0 +1,462 @@
/**
******************************************************************************
* @file stm32h7xx_hal_uart_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_UART_EX_H
#define __STM32H7xx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UART Word Length
* @{
*/
#define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B ((uint32_t)0x00000000U) /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000U) /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B ((uint32_t)USART_CR2_ADDM7) /*!< 7-bit long wake-up address */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__: specifies the UART Handle.
* @param __CLOCKSOURCE__: output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART2CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART2CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_USART3CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART3CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART4CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART4CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if ((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART5CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART5CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
switch(__HAL_RCC_GET_USART6_SOURCE()) \
{ \
case RCC_USART6CLKSOURCE_D2PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2; \
break; \
case RCC_USART6CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_USART6CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_USART6CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART6CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_USART6CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART7) \
{ \
switch(__HAL_RCC_GET_UART7_SOURCE()) \
{ \
case RCC_UART7CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART7CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART7CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART7CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART7CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART7CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART8) \
{ \
switch(__HAL_RCC_GET_UART8_SOURCE()) \
{ \
case RCC_UART8CLKSOURCE_D2PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1; \
break; \
case RCC_UART8CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_UART8CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_UART8CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART8CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_UART8CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_D3PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_PLL2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2; \
break; \
case RCC_LPUART1CLKSOURCE_PLL3: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_CSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
} \
} \
} while(0)
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__: specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FF ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007F ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007F ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003F ; \
} \
} \
} while(0)
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__: UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__: UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_UART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h
+1071
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart_ex.h
+159
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@@ -0,0 +1,159 @@
/**
******************************************************************************
* @file stm32h7xx_hal_usart_ex.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_USART_EX_H
#define __STM32H7xx_HAL_USART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup USARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
* @{
*/
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B ((uint32_t)0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
* @{
*/
/** @brief Compute the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__: specifies the USART Handle.
* @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FF ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FF ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007F ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007F ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003F ; \
} \
} \
} while(0)
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__: USART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_USART_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_wwdg.h
+294
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/**
******************************************************************************
* @file stm32h7xx_hal_wwdg.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_HAL_WWDG_H
#define __STM32H7xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
/**
* @brief WWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
}WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
typedef struct
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
}WWDG_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
*/
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
#define WWDG_PRESCALER_1 ((uint32_t)(0x00000000U)) /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 ((uint32_t)(WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 ((uint32_t)(WWDG_CFR_WDGTB1)) /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 ((uint32_t)(WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/8 */
#define WWDG_PRESCALER_16 ((uint32_t)(WWDG_CFR_WDGTB2)) /*!< WWDG counter clock = (PCLK1/4096)/16 */
#define WWDG_PRESCALER_32 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/32 */
#define WWDG_PRESCALER_64 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1)) /*!< WWDG counter clock = (PCLK1/4096)/64 */
#define WWDG_PRESCALER_128 ((uint32_t)(WWDG_CFR_WDGTB2|WWDG_CFR_WDGTB1|WWDG_CFR_WDGTB0)) /*!< WWDG counter clock = (PCLK1/4096)/128 */
/**
* @}
*/
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
((__PRESCALER__) == WWDG_PRESCALER_2) || \
((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8) || \
((__PRESCALER__) == WWDG_PRESCALER_16) || \
((__PRESCALER__) == WWDG_PRESCALER_32) || \
((__PRESCALER__) == WWDG_PRESCALER_64) || \
((__PRESCALER__) == WWDG_PRESCALER_128))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W6) && ((__WINDOW__) <= WWDG_CFR_W))
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T6) && ((__COUNTER__) <= WWDG_CR_T))
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
((__MODE__) == WWDG_EWI_DISABLE))
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
*/
/**
* @brief Enable the WWDG peripheral.
* @param __HANDLE__ WWDG handle
* @retval None
*/
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
* @brief Enable the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
* @brief Check whether the selected WWDG interrupt has occurred or not.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
/** @brief Clear the WWDG interrupt pending bits.
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
* @brief Check whether the specified WWDG flag is set or not.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the WWDG's pending flags.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(uint32_t)(__FLAG__))
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
* @param __HANDLE__ WWDG Handle.
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup WWDG_Exported_Functions
* @{
*/
/** @addtogroup WWDG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_HAL_WWDG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_delayblock.h
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/**
******************************************************************************
* @file stm32h7xx_ll_delayblock.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of Delay Block module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_LL_DLYB_H
#define __STM32H7xx_LL_DLYB_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL_Driver
* @{
*/
/** @addtogroup DELAYBLOCK_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DELAYBLOCK_LL_Exported_Types DELAYBLOCK_LL Exported Types
* @{
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DLYB_Exported_Constants Delay Block Exported Constants
* @{
*/
#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */
/** @defgroup DLYB_Instance DLYB Instance
* @{
*/
#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
((INSTANCE) == DLYB_SDMMC2) || \
((INSTANCE) == DLYB_QUADSPI))
/**
* @}
*/
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup HAL_DELAYBLOCK_LL_Group3 Delay Block functions
* @{
*/
HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *dlyb);
HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *dlyb);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_LL_DLYB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40-h7/Drivers/STM32H7xx_HAL_Driver/Inc/stm32h7xx_ll_usb.h
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/**
******************************************************************************
* @file stm32h7xx_ll_usb.h
* @author MCD Application Team
* @version V1.2.0
* @date 29-December-2017
* @brief Header file of USB Core HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H7xx_LL_USB_H
#define __STM32H7xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h7xx_hal_def.h"
/** @addtogroup STM32H7xx_HAL
* @{
*/
/** @addtogroup USB_Core
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USB Mode definition
*/
typedef enum
{
USB_OTG_DEVICE_MODE = 0U,
USB_OTG_HOST_MODE = 1U,
USB_OTG_DRD_MODE = 2U
}USB_OTG_ModeTypeDef;
/**
* @brief URB States definition
*/
typedef enum {
URB_IDLE = 0U,
URB_DONE,
URB_NOTREADY,
URB_NYET,
URB_ERROR,
URB_STALL
}USB_OTG_URBStateTypeDef;
/**
* @brief Host channel States definition
*/
typedef enum {
HC_IDLE = 0U,
HC_XFRC,
HC_HALTED,
HC_NAK,
HC_NYET,
HC_STALL,
HC_XACTERR,
HC_BBLERR,
HC_DATATGLERR
}USB_OTG_HCStateTypeDef;
/**
* @brief PCD Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t Host_channels; /*!< Host Channels number.
This parameter Depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref USB_Core_Speed_ */
uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA. */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size.
This parameter can be any value of @ref USB_EP0_MPS_ */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref USB_Core_PHY_ */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable the low power mode. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
uint32_t lpm_enable; /*!< Enable or disable Link Power Management. */
uint32_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */
uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */
uint32_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */
}USB_OTG_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type_ */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t even_odd_frame; /*!< IFrame parity
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t tx_fifo_num; /*!< Transmission FIFO number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
}USB_OTG_EPTypeDef;
typedef struct
{
uint8_t dev_addr ; /*!< USB device address.
This parameter must be a number between Min_Data = 1 and Max_Data = 255 */
uint8_t ch_num; /*!< Host channel number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_num; /*!< Endpoint number.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t ep_is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t speed; /*!< USB Host speed.
This parameter can be any value of @ref USB_Core_Speed_ */
uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */
uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */
uint8_t ep_type; /*!< Endpoint Type.
This parameter can be any value of @ref USB_EP_Type_ */
uint16_t max_packet; /*!< Endpoint Max packet size.
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t data_pid; /*!< Initial data PID.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */
uint32_t xfer_len; /*!< Current transfer length. */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */
uint8_t toggle_in; /*!< IN transfer current toggle flag.
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t toggle_out; /*!< OUT transfer current toggle flag
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */
uint32_t ErrCnt; /*!< Host channel error count.*/
USB_OTG_URBStateTypeDef urb_state; /*!< URB state.
This parameter can be any value of @ref USB_OTG_URBStateTypeDef */
USB_OTG_HCStateTypeDef state; /*!< Host Channel state.
This parameter can be any value of @ref USB_OTG_HCStateTypeDef */
}USB_OTG_HCTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup USB_Core_Mode_ USB Core Mode
* @{
*/
#define USB_OTG_MODE_DEVICE 0U
#define USB_OTG_MODE_HOST 1U
#define USB_OTG_MODE_DRD 2U
/**
* @}
*/
/** @defgroup USB_Core_Speed_ USB Core Speed
* @{
*/
#define USB_OTG_SPEED_HIGH 0U
#define USB_OTG_SPEED_HIGH_IN_FULL 1U
#define USB_OTG_SPEED_LOW 2U
#define USB_OTG_SPEED_FULL 3U
/**
* @}
*/
/** @defgroup USB_Core_PHY_ USB Core PHY
* @{
*/
#define USB_OTG_ULPI_PHY 1U
#define USB_OTG_EMBEDDED_PHY 2U
/**
* @}
*/
/** @defgroup USB_Core_MPS_ USB Core MPS
* @{
*/
#define USB_OTG_HS_MAX_PACKET_SIZE 512U
#define USB_OTG_FS_MAX_PACKET_SIZE 64U
#define USB_OTG_MAX_EP0_SIZE 64U
/**
* @}
*/
/** @defgroup USB_Core_Phy_Frequency_ USB Core Phy Frequency
* @{
*/
#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0 << 1)
#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1 << 1)
#define DSTS_ENUMSPD_LS_PHY_6MHZ (2 << 1)
#define DSTS_ENUMSPD_FS_PHY_48MHZ (3 << 1)
/**
* @}
*/
/** @defgroup USB_CORE_Frame_Interval_ USB CORE Frame Interval
* @{
*/
#define DCFG_FRAME_INTERVAL_80 0U
#define DCFG_FRAME_INTERVAL_85 1U
#define DCFG_FRAME_INTERVAL_90 2U
#define DCFG_FRAME_INTERVAL_95 3U
/**
* @}
*/
/** @defgroup USB_EP0_MPS_ USB EP0 MPS
* @{
*/
#define DEP0CTL_MPS_64 0U
#define DEP0CTL_MPS_32 1U
#define DEP0CTL_MPS_16 2U
#define DEP0CTL_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_EP_Speed_ USB EP Speed
* @{
*/
#define EP_SPEED_LOW 0U
#define EP_SPEED_FULL 1U
#define EP_SPEED_HIGH 2U
/**
* @}
*/
/** @defgroup USB_EP_Type_ USB EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_STS_Defines_ USB STS Defines
* @{
*/
#define STS_GOUT_NAK 1U
#define STS_DATA_UPDT 2U
#define STS_XFER_COMP 3U
#define STS_SETUP_COMP 4U
#define STS_SETUP_UPDT 6U
/**
* @}
*/
/** @defgroup HCFG_SPEED_Defines_ HCFG SPEED Defines
* @{
*/
#define HCFG_30_60_MHZ 0U
#define HCFG_48_MHZ 1U
#define HCFG_6_MHZ 2U
/**
* @}
*/
/** @defgroup HPRT0_PRTSPD_SPEED_Defines_ HPRT0 PRTSPD SPEED Defines
* @{
*/
#define HPRT0_PRTSPD_HIGH_SPEED 0U
#define HPRT0_PRTSPD_FULL_SPEED 1U
#define HPRT0_PRTSPD_LOW_SPEED 2U
/**
* @}
*/
#define HCCHAR_CTRL 0U
#define HCCHAR_ISOC 1U
#define HCCHAR_BULK 2U
#define HCCHAR_INTR 3U
#define HC_PID_DATA0 0U
#define HC_PID_DATA2 1U
#define HC_PID_DATA1 2U
#define HC_PID_SETUP 3U
#define GRXSTS_PKTSTS_IN 2U
#define GRXSTS_PKTSTS_IN_XFER_COMP 3U
#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U
#define GRXSTS_PKTSTS_CH_HALTED 7U
#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE))
#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))
#define USBx_DFIFO(i) *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
#define USBx_HOST ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))
#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))
/* Exported functions --------------------------------------------------------*/
HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
void * USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
uint8_t speed,
uint8_t ep_type,
uint16_t mps);
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H7xx_LL_USB_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/