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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal.c
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/**
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The common HAL driver contains a set of generic and common APIs that can be
used by the PPP peripheral drivers and the user to start using the HAL.
[..]
The HAL contains two APIs' categories:
(+) Common HAL APIs
(+) Services HAL APIs
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup HAL HAL
* @brief HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup HAL_Private_Constants
* @{
*/
/**
* @brief STM32F7xx HAL Driver version number V1.2.0
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
|(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\
|(__STM32F7xx_HAL_VERSION_RC))
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup HAL_Private_Variables
* @{
*/
__IO uint32_t uwTick;
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HAL_Exported_Functions HAL Exported Functions
* @{
*/
/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface the NVIC allocation and initial clock
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
(+) de-Initializes common part of the HAL
(+) Configure The time base source to have 1ms time base with a dedicated
Tick interrupt priority.
(++) Systick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
handled in milliseconds basis.
(++) Time base configuration function (HAL_InitTick ()) is called automatically
at the beginning of the program after reset by HAL_Init() or at any time
when clock is configured, by HAL_RCC_ClockConfig().
(++) Source of time base is configured to generate interrupts at regular
time intervals. Care must be taken if HAL_Delay() is called from a
peripheral ISR process, the Tick interrupt line must have higher priority
(numerically lower) than the peripheral interrupt. Otherwise the caller
ISR process will be blocked.
(++) functions affecting time base configurations are declared as __weak
to make override possible in case of other implementations in user file.
@endverbatim
* @{
*/
/**
* @brief This function is used to initialize the HAL Library; it must be the first
* instruction to be executed in the main program (before to call any other
* HAL function), it performs the following:
* Configure the Flash prefetch, and instruction cache through ART accelerator.
* Configures the SysTick to generate an interrupt each 1 millisecond,
* which is clocked by the HSI (at this stage, the clock is not yet
* configured and thus the system is running from the internal HSI at 16 MHz).
* Set NVIC Group Priority to 4.
* Calls the HAL_MspInit() callback function defined in user file
* "stm32f7xx_hal_msp.c" to do the global low level hardware initialization
*
* @note SysTick is used as time base for the HAL_Delay() function, the application
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
/* Configure Flash prefetch and Instruction cache through ART accelerator */
#if (ART_ACCLERATOR_ENABLE != 0)
__HAL_FLASH_ART_ENABLE();
#endif /* ART_ACCLERATOR_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
/* Init the low level hardware */
HAL_MspInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief This function de-Initializes common part of the HAL and stops the systick.
* This function is optional.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DeInit(void)
{
/* Reset of all peripherals */
__HAL_RCC_APB1_FORCE_RESET();
__HAL_RCC_APB1_RELEASE_RESET();
__HAL_RCC_APB2_FORCE_RESET();
__HAL_RCC_APB2_RELEASE_RESET();
__HAL_RCC_AHB1_FORCE_RESET();
__HAL_RCC_AHB1_RELEASE_RESET();
__HAL_RCC_AHB2_FORCE_RESET();
__HAL_RCC_AHB2_RELEASE_RESET();
__HAL_RCC_AHB3_FORCE_RESET();
__HAL_RCC_AHB3_RELEASE_RESET();
/* De-Init the low level hardware */
HAL_MspDeInit();
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the MSP.
* @retval None
*/
__weak void HAL_MspDeInit(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function configures the source of the time base.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
* The the SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
HAL_SYSTICK_Config(SystemCoreClock/1000);
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
* @brief HAL Control functions
*
@verbatim
===============================================================================
##### HAL Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Provide a tick value in millisecond
(+) Provide a blocking delay in millisecond
(+) Suspend the time base source interrupt
(+) Resume the time base source interrupt
(+) Get the HAL API driver version
(+) Get the device identifier
(+) Get the device revision identifier
(+) Enable/Disable Debug module during SLEEP mode
(+) Enable/Disable Debug module during STOP mode
(+) Enable/Disable Debug module during STANDBY mode
@endverbatim
* @{
*/
/**
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
* in Systick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick++;
}
/**
* @brief Provides a tick value in millisecond.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @param Delay: specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(__IO uint32_t Delay)
{
uint32_t tickstart = 0;
tickstart = HAL_GetTick();
while((HAL_GetTick() - tickstart) < Delay)
{
}
}
/**
* @brief Suspend Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
* is called, the SysTick interrupt will be disabled and so Tick increment
* is suspended.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_SuspendTick(void)
{
/* Disable SysTick Interrupt */
SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Resume Tick increment.
* @note In the default implementation , SysTick timer is the source of time base. It is
* used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
* is called, the SysTick interrupt will be enabled and so Tick increment
* is resumed.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_ResumeTick(void)
{
/* Enable SysTick Interrupt */
SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
}
/**
* @brief Returns the HAL revision
* @retval version : 0xXYZR (8bits for each decimal, R for RC)
*/
uint32_t HAL_GetHalVersion(void)
{
return __STM32F7xx_HAL_VERSION;
}
/**
* @brief Returns the device revision identifier.
* @retval Device revision identifier
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE) >> 16U);
}
/**
* @brief Returns the device identifier.
* @retval Device identifier
*/
uint32_t HAL_GetDEVID(void)
{
return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @retval None
*/
void HAL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Enables the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
* voltage ranges from 2.4 to 3.6 V.
* @retval None
*/
void HAL_EnableCompensationCell(void)
{
SYSCFG->CMPCR |= SYSCFG_CMPCR_CMP_PD;
}
/**
* @brief Power-down the I/O Compensation Cell.
* @note The I/O compensation cell can be used only when the device supply
* voltage ranges from 2.4 to 3.6 V.
* @retval None
*/
void HAL_DisableCompensationCell(void)
{
SYSCFG->CMPCR &= (uint32_t)~((uint32_t)SYSCFG_CMPCR_CMP_PD);
}
/**
* @brief Enables the FMC Memory Mapping Swapping.
*
* @note SDRAM is accessible at 0x60000000
* and NOR/RAM is accessible at 0xC0000000
*
* @retval None
*/
void HAL_EnableFMCMemorySwapping(void)
{
SYSCFG->MEMRMP |= SYSCFG_MEMRMP_SWP_FMC_0;
}
/**
* @brief Disables the FMC Memory Mapping Swapping
*
* @note SDRAM is accessible at 0xC0000000 (default mapping)
* and NOR/RAM is accessible at 0x60000000 (default mapping)
*
* @retval None
*/
void HAL_DisableFMCMemorySwapping(void)
{
SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/**
* @brief Enable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
*
* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))
*
* @retval None
*/
void HAL_EnableMemorySwappingBank(void)
{
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
}
/**
* @brief Disable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
*
* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM))
*
* @retval None
*/
void HAL_DisableMemorySwappingBank(void)
{
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_adc.c
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/**
******************************************************************************
* @file stm32f7xx_hal_cec.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief CEC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the High Definition Multimedia Interface
* Consumer Electronics Control Peripheral (CEC).
* + Initialization and de-initialization function
* + IO operation function
* + Peripheral Control function
*
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The CEC HAL driver can be used as follow:
(#) Declare a CEC_HandleTypeDef handle structure.
(#) Initialize the CEC low level resources by implementing the HAL_CEC_MspInit ()API:
(##) Enable the CEC interface clock.
(##) CEC pins configuration:
(+++) Enable the clock for the CEC GPIOs.
(+++) Configure these CEC pins as alternate function pull-up.
(##) NVIC configuration if you need to use interrupt process (HAL_CEC_Transmit_IT()
and HAL_CEC_Receive_IT() APIs):
(+++) Configure the CEC interrupt priority.
(+++) Enable the NVIC CEC IRQ handle.
(+++) The specific CEC interrupts (Transmission complete interrupt,
RXNE interrupt and Error Interrupts) will be managed using the macros
__HAL_CEC_ENABLE_IT() and __HAL_CEC_DISABLE_IT() inside the transmit
and receive process.
(#) Program the Signal Free Time (SFT) and SFT option, Tolerance, reception stop in
in case of Bit Rising Error, Error-Bit generation conditions, device logical
address and Listen mode in the hcec Init structure.
(#) Initialize the CEC registers by calling the HAL_CEC_Init() API.
[..]
(@) This API (HAL_CEC_Init()) configures also the low level Hardware (GPIO, CLOCK, CORTEX...etc)
by calling the customed HAL_CEC_MspInit() API.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup CEC CEC
* @brief HAL CEC module driver
* @{
*/
#ifdef HAL_CEC_MODULE_ENABLED
#if defined (CEC)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup CEC_Private_Constants CEC Private Constants
* @{
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{
*/
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @defgroup CEC_Exported_Functions CEC Exported Functions
* @{
*/
/** @defgroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the CEC
(+) The following parameters need to be configured:
(++) SignalFreeTime
(++) Tolerance
(++) BRERxStop (RX stopped or not upon Bit Rising Error)
(++) BREErrorBitGen (Error-Bit generation in case of Bit Rising Error)
(++) LBPEErrorBitGen (Error-Bit generation in case of Long Bit Period Error)
(++) BroadcastMsgNoErrorBitGen (Error-bit generation in case of broadcast message error)
(++) SignalFreeTimeOption (SFT Timer start definition)
(++) OwnAddress (CEC device address)
(++) ListenMode
@endverbatim
* @{
*/
/**
* @brief Initializes the CEC mode according to the specified
* parameters in the CEC_InitTypeDef and creates the associated handle .
* @param hcec: CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if((hcec == NULL) ||(hcec->Init.RxBuffer == NULL))
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime));
assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance));
assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop));
assert_param(IS_CEC_BREERRORBITGEN(hcec->Init.BREErrorBitGen));
assert_param(IS_CEC_LBPEERRORBITGEN(hcec->Init.LBPEErrorBitGen));
assert_param(IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(hcec->Init.BroadcastMsgNoErrorBitGen));
assert_param(IS_CEC_SFTOP(hcec->Init.SignalFreeTimeOption));
assert_param(IS_CEC_LISTENING_MODE(hcec->Init.ListenMode));
assert_param(IS_CEC_OWN_ADDRESS(hcec->Init.OwnAddress));
if(hcec->gState == HAL_CEC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcec->Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK */
HAL_CEC_MspInit(hcec);
}
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Write to CEC Control Register */
hcec->Instance->CFGR = hcec->Init.SignalFreeTime | hcec->Init.Tolerance | hcec->Init.BRERxStop|\
hcec->Init.BREErrorBitGen | hcec->Init.LBPEErrorBitGen | hcec->Init.BroadcastMsgNoErrorBitGen |\
hcec->Init.SignalFreeTimeOption |((uint32_t)(hcec->Init.OwnAddress)<<16U) |\
hcec->Init.ListenMode;
/* Enable the following CEC Transmission/Reception interrupts as
* well as the following CEC Transmission/Reception Errors interrupts
* Rx Byte Received IT
* End of Reception IT
* Rx overrun
* Rx bit rising error
* Rx short bit period error
* Rx long bit period error
* Rx missing acknowledge
* Tx Byte Request IT
* End of Transmission IT
* Tx Missing Acknowledge IT
* Tx-Error IT
* Tx-Buffer Underrun IT
* Tx arbitration lost */
__HAL_CEC_ENABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
/* Enable the CEC Peripheral */
__HAL_CEC_ENABLE(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_READY;
hcec->RxState = HAL_CEC_STATE_READY;
return HAL_OK;
}
/**
* @brief DeInitializes the CEC peripheral
* @param hcec: CEC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
{
/* Check the CEC handle allocation */
if(hcec == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance));
hcec->gState = HAL_CEC_STATE_BUSY;
/* DeInit the low level hardware */
HAL_CEC_MspDeInit(hcec);
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
/* Clear Flags */
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXEND|CEC_FLAG_TXBR|CEC_FLAG_RXBR|CEC_FLAG_RXEND|CEC_ISR_ALL_ERROR);
/* Disable the following CEC Transmission/Reception interrupts as
* well as the following CEC Transmission/Reception Errors interrupts
* Rx Byte Received IT
* End of Reception IT
* Rx overrun
* Rx bit rising error
* Rx short bit period error
* Rx long bit period error
* Rx missing acknowledge
* Tx Byte Request IT
* End of Transmission IT
* Tx Missing Acknowledge IT
* Tx-Error IT
* Tx-Buffer Underrun IT
* Tx arbitration lost */
__HAL_CEC_DISABLE_IT(hcec, CEC_IT_RXBR|CEC_IT_RXEND|CEC_IER_RX_ALL_ERR|CEC_IT_TXBR|CEC_IT_TXEND|CEC_IER_TX_ALL_ERR);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->gState = HAL_CEC_STATE_RESET;
hcec->RxState = HAL_CEC_STATE_RESET;
/* Process Unlock */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
/**
* @brief Initializes the Own Address of the CEC device
* @param hcec: CEC handle
* @param CEC_OwnAddress: The CEC own address.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
{
/* Check the parameters */
assert_param(IS_CEC_OWN_ADDRESS(CEC_OwnAddress));
if ((hcec->gState == HAL_CEC_STATE_READY) && (hcec->RxState == HAL_CEC_STATE_READY))
{
/* Process Locked */
__HAL_LOCK(hcec);
hcec->gState = HAL_CEC_STATE_BUSY;
/* Disable the Peripheral */
__HAL_CEC_DISABLE(hcec);
if(CEC_OwnAddress != CEC_OWN_ADDRESS_NONE)
{
hcec->Instance->CFGR |= ((uint32_t)CEC_OwnAddress<<16);
}
else
{
hcec->Instance->CFGR &= ~(CEC_CFGR_OAR);
}
hcec->gState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcec);
/* Enable the Peripheral */
__HAL_CEC_ENABLE(hcec);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief CEC MSP Init
* @param hcec: CEC handle
* @retval None
*/
__weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspInit can be implemented in the user file
*/
}
/**
* @brief CEC MSP DeInit
* @param hcec: CEC handle
* @retval None
*/
__weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CEC_Exported_Functions_Group2 Input and Output operation functions
* @brief CEC Transmit/Receive functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the CEC data transfers.
(#) The CEC handle must contain the initiator (TX side) and the destination (RX side)
logical addresses (4-bit long addresses, 0xF for broadcast messages destination)
(#) The communication is performed using Interrupts.
These API's return the HAL status.
The end of the data processing will be indicated through the
dedicated CEC IRQ when using Interrupt mode.
The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks
will be executed respectively at the end of the transmit or Receive process
The HAL_CEC_ErrorCallback() user callback will be executed when a communication
error is detected
(#) API's with Interrupt are :
(+) HAL_CEC_Transmit_IT()
(+) HAL_CEC_IRQHandler()
(#) A set of User Callbacks are provided:
(+) HAL_CEC_TxCpltCallback()
(+) HAL_CEC_RxCpltCallback()
(+) HAL_CEC_ErrorCallback()
@endverbatim
* @{
*/
/**
* @brief Send data in interrupt mode
* @param hcec: CEC handle
* @param InitiatorAddress: Initiator address
* @param DestinationAddress: destination logical address
* @param pData: pointer to input byte data buffer
* @param Size: amount of data to be sent in bytes (without counting the header).
* 0 means only the header is sent (ping operation).
* Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size)
{
/* if the IP isn't already busy and if there is no previous transmission
already pending due to arbitration lost */
if (hcec->gState == HAL_CEC_STATE_READY)
{
if((pData == NULL ) && (Size > 0))
{
return HAL_ERROR;
}
assert_param(IS_CEC_ADDRESS(DestinationAddress));
assert_param(IS_CEC_ADDRESS(InitiatorAddress));
assert_param(IS_CEC_MSGSIZE(Size));
/* Process Locked */
__HAL_LOCK(hcec);
hcec->pTxBuffPtr = pData;
hcec->gState = HAL_CEC_STATE_BUSY_TX;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
/* initialize the number of bytes to send,
* 0 means only one header is sent (ping operation) */
hcec->TxXferCount = Size;
/* in case of no payload (Size = 0), sender is only pinging the system;
Set TX End of Message (TXEOM) bit, must be set before writing data to TXDR */
if (Size == 0)
{
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
}
/* send header block */
hcec->Instance->TXDR = ((uint8_t)(InitiatorAddress << CEC_INITIATOR_LSB_POS) |(uint8_t) DestinationAddress);
/* Set TX Start of Message (TXSOM) bit */
__HAL_CEC_FIRST_BYTE_TX_SET(hcec);
/* Process Unlocked */
__HAL_UNLOCK(hcec);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Get size of the received frame.
* @param hcec: CEC handle
* @retval Frame size
*/
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
{
return hcec->RxXferSize;
}
/**
* @brief Change Rx Buffer.
* @param hcec: CEC handle
* @param Rxbuffer: Rx Buffer
* @note This function can be called only inside the HAL_CEC_RxCpltCallback()
* @retval Frame size
*/
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
{
hcec->Init.RxBuffer = Rxbuffer;
}
/**
* @brief This function handles CEC interrupt requests.
* @param hcec: CEC handle
* @retval None
*/
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
{
/* save interrupts register for further error or interrupts handling purposes */
uint32_t reg = 0;
reg = hcec->Instance->ISR;
/* ----------------------------Arbitration Lost Management----------------------------------*/
/* CEC TX arbitration error interrupt occurred --------------------------------------*/
if((reg & CEC_FLAG_ARBLST) != RESET)
{
hcec->ErrorCode = HAL_CEC_ERROR_ARBLST;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST);
}
/* ----------------------------Rx Management----------------------------------*/
/* CEC RX byte received interrupt ---------------------------------------------------*/
if((reg & CEC_FLAG_RXBR) != RESET)
{
/* reception is starting */
hcec->RxState = HAL_CEC_STATE_BUSY_RX;
hcec->RxXferSize++;
/* read received byte */
*hcec->Init.RxBuffer++ = hcec->Instance->RXDR;
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXBR);
}
/* CEC RX end received interrupt ---------------------------------------------------*/
if((reg & CEC_FLAG_RXEND) != RESET)
{
/* clear IT */
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND);
/* Rx process is completed, restore hcec->RxState to Ready */
hcec->RxState = HAL_CEC_STATE_READY;
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
hcec->Init.RxBuffer-=hcec->RxXferSize;
HAL_CEC_RxCpltCallback(hcec, hcec->RxXferSize);
hcec->RxXferSize = 0;
}
/* ----------------------------Tx Management----------------------------------*/
/* CEC TX byte request interrupt ------------------------------------------------*/
if((reg & CEC_FLAG_TXBR) != RESET)
{
if (hcec->TxXferCount == 0)
{
/* if this is the last byte transmission, set TX End of Message (TXEOM) bit */
__HAL_CEC_LAST_BYTE_TX_SET(hcec);
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
}
else
{
hcec->Instance->TXDR = *hcec->pTxBuffPtr++;
hcec->TxXferCount--;
}
/* clear Tx-Byte request flag */
__HAL_CEC_CLEAR_FLAG(hcec,CEC_FLAG_TXBR);
}
/* CEC TX end interrupt ------------------------------------------------*/
if((reg & CEC_FLAG_TXEND) != RESET)
{
__HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND);
/* Tx process is ended, restore hcec->gState to Ready */
hcec->gState = HAL_CEC_STATE_READY;
/* Call the Process Unlocked before calling the Tx call back API to give the possibility to
start again the Transmission under the Tx call back API */
__HAL_UNLOCK(hcec);
hcec->ErrorCode = HAL_CEC_ERROR_NONE;
HAL_CEC_TxCpltCallback(hcec);
}
/* ----------------------------Rx/Tx Error Management----------------------------------*/
if ((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != 0)
{
hcec->ErrorCode = reg;
__HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR|HAL_CEC_ERROR_BRE|CEC_FLAG_LBPE|CEC_FLAG_SBPE|HAL_CEC_ERROR_RXACKE|HAL_CEC_ERROR_TXUDR|HAL_CEC_ERROR_TXERR|HAL_CEC_ERROR_TXACKE);
if((reg & (CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE)) != RESET)
{
hcec->Init.RxBuffer-=hcec->RxXferSize;
hcec->RxXferSize = 0;
hcec->RxState = HAL_CEC_STATE_READY;
}
else if (((reg & (CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)) != RESET) && ((reg & CEC_ISR_ARBLST) == RESET))
{
/* Set the CEC state ready to be able to start again the process */
hcec->gState = HAL_CEC_STATE_READY;
}
/* Error Call Back */
HAL_CEC_ErrorCallback(hcec);
}
}
/**
* @brief Tx Transfer completed callback
* @param hcec: CEC handle
* @retval None
*/
__weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_TxCpltCallback can be implemented in the user file
*/
}
/**
* @brief Rx Transfer completed callback
* @param hcec: CEC handle
* @param RxFrameSize: Size of frame
* @retval None
*/
__weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
UNUSED(RxFrameSize);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_RxCpltCallback can be implemented in the user file
*/
}
/**
* @brief CEC error callbacks
* @param hcec: CEC handle
* @retval None
*/
__weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcec);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CEC_ErrorCallback can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup CEC_Exported_Functions_Group3 Peripheral Control function
* @brief CEC control functions
*
@verbatim
===============================================================================
##### Peripheral Control function #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the CEC.
(+) HAL_CEC_GetState() API can be helpful to check in run-time the state of the CEC peripheral.
(+) HAL_CEC_GetError() API can be helpful to check in run-time the error of the CEC peripheral.
@endverbatim
* @{
*/
/**
* @brief return the CEC state
* @param hcec: pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC module.
* @retval HAL state
*/
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
{
uint32_t temp1= 0x00U, temp2 = 0x00U;
temp1 = hcec->gState;
temp2 = hcec->RxState;
return (HAL_CEC_StateTypeDef)(temp1 | temp2);
}
/**
* @brief Return the CEC error code
* @param hcec : pointer to a CEC_HandleTypeDef structure that contains
* the configuration information for the specified CEC.
* @retval CEC Error Code
*/
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec)
{
return hcec->ErrorCode;
}
/**
* @}
*/
/**
* @}
*/
#endif /* CEC */
#endif /* HAL_CEC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_cortex.c
Executable
+523
View File
@@ -0,0 +1,523 @@
/**
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
*** How to configure Interrupts using CORTEX HAL driver ***
===========================================================
[..]
This section provides functions allowing to configure the NVIC interrupts (IRQ).
The Cortex-M4 exceptions are managed by CMSIS functions.
(#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
function according to the following table.
(#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
(#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
(#) please refer to programming manual for details in how to configure priority.
-@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible.
The pending IRQ priority will be managed only by the sub priority.
-@- IRQ priority order (sorted by highest to lowest priority):
(+@) Lowest preemption priority
(+@) Lowest sub priority
(+@) Lowest hardware priority (IRQ number)
[..]
*** How to configure Systick using CORTEX HAL driver ***
========================================================
[..]
Setup SysTick Timer for time base.
(+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
is a CMSIS function that:
(++) Configures the SysTick Reload register with value passed as function parameter.
(++) Configures the SysTick IRQ priority to the lowest value (0x0F).
(++) Resets the SysTick Counter register.
(++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
(++) Enables the SysTick Interrupt.
(++) Starts the SysTick Counter.
(+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
__HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
inside the stm32f7xx_hal_cortex.h file.
(+) You can change the SysTick IRQ priority by calling the
HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
(+) To adjust the SysTick time base, use the following formula:
Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
(++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
(++) Reload Value should not exceed 0xFFFFFF
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
#ifdef HAL_CORTEX_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..]
This section provides the CORTEX HAL driver functions allowing to configure Interrupts
Systick functionalities
@endverbatim
* @{
*/
/**
* @brief Sets the priority grouping field (preemption priority and subpriority)
* using the required unlock sequence.
* @param PriorityGroup: The priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @param PreemptPriority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority
* @param SubPriority: the subpriority level for the IRQ channel.
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t prioritygroup = 0x00;
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
* function should be called before.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void HAL_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control the CORTEX
(NVIC, SYSTICK, MPU) functionalities.
@endverbatim
* @{
*/
#if (__MPU_PRESENT == 1)
/**
* @brief Disables the MPU
* @retval None
*/
void HAL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable fault exceptions */
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
/* Disable the MPU and clear the control register*/
MPU->CTRL = 0;
}
/**
* @brief Enables the MPU
* @param MPU_Control: Specifies the control mode of the MPU during hard fault,
* NMI, FAULTMASK and privileged access to the default memory
* This parameter can be one of the following values:
* @arg MPU_HFNMI_PRIVDEF_NONE
* @arg MPU_HARDFAULT_NMI
* @arg MPU_PRIVILEGED_DEFAULT
* @arg MPU_HFNMI_PRIVDEF
* @retval None
*/
void HAL_MPU_Enable(uint32_t MPU_Control)
{
/* Enable the MPU */
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
/* Enable fault exceptions */
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
/* Ensure MPU setting take effects */
__DSB();
__ISB();
}
/**
* @brief Initializes and configures the Region and the memory to be protected.
* @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
* the initialization and configuration information.
* @retval None
*/
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
{
/* Check the parameters */
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
/* Set the Region number */
MPU->RNR = MPU_Init->Number;
if ((MPU_Init->Enable) != RESET)
{
/* Check the parameters */
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
MPU->RBAR = MPU_Init->BaseAddress;
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
}
else
{
MPU->RBAR = 0x00;
MPU->RASR = 0x00;
}
}
#endif /* __MPU_PRESENT */
/**
* @brief Gets the priority grouping field from the NVIC Interrupt Controller.
* @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
*/
uint32_t HAL_NVIC_GetPriorityGrouping(void)
{
/* Get the PRIGROUP[10:8] field value */
return NVIC_GetPriorityGrouping();
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @param PriorityGroup: the priority grouping bits length.
* This parameter can be one of the following values:
* @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
* 4 bits for subpriority
* @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
* 3 bits for subpriority
* @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
* 2 bits for subpriority
* @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
* 1 bits for subpriority
* @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
* 0 bits for subpriority
* @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
* @param pSubPriority: Pointer on the Subpriority value (starting from 0).
* @retval None
*/
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
{
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Get priority for Cortex-M system or device specific interrupts */
NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Gets Pending Interrupt (reads the pending register in the NVIC
* and returns the pending bit for the specified interrupt).
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if pending else 0 */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval None
*/
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Clear pending interrupt */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h))
* @retval status: - 0 Interrupt status is not pending.
* - 1 Interrupt status is pending.
*/
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
{
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Return 1 if active else 0 */
return NVIC_GetActive(IRQn);
}
/**
* @brief Configures the SysTick clock source.
* @param CLKSource: specifies the SysTick clock source.
* This parameter can be one of the following values:
* @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
* @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
* @retval None
*/
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
{
/* Check the parameters */
assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
}
}
/**
* @brief This function handles SYSTICK interrupt request.
* @retval None
*/
void HAL_SYSTICK_IRQHandler(void)
{
HAL_SYSTICK_Callback();
}
/**
* @brief SYSTICK callback.
* @retval None
*/
__weak void HAL_SYSTICK_Callback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SYSTICK_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CORTEX_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc.c
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/**
******************************************************************************
* @file stm32f7xx_hal_crc.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
===============================================================================
##### CRC How to use this driver #####
===============================================================================
[..]
(#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE();
(#) Initialize CRC calculator
(++) specify generating polynomial (IP default or non-default one)
(++) specify initialization value (IP default or non-default one)
(++) specify input data format
(++) specify input or output data inversion mode if any
(#) Use HAL_CRC_Accumulate() function to compute the CRC value of the
input data buffer starting with the previously computed CRC as
initialization value
(#) Use HAL_CRC_Calculate() function to compute the CRC value of the
input data buffer starting with the defined initialization value
(default or non-default) to initiate CRC calculation
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup CRC CRC
* @brief CRC HAL module driver.
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength);
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength);
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup HAL_CRC_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the CRC according to the specified parameters
in the CRC_InitTypeDef and create the associated handle
(+) DeInitialize the CRC peripheral
(+) Initialize the CRC MSP
(+) DeInitialize CRC MSP
@endverbatim
* @{
*/
/**
* @brief Initialize the CRC according to the specified
* parameters in the CRC_InitTypeDef and create the associated handle.
* @param hcrc: CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if(hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
if(hcrc->State == HAL_CRC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hcrc->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_CRC_MspInit(hcrc);
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* check whether or not non-default generating polynomial has been
* picked up by user */
assert_param(IS_DEFAULT_POLYNOMIAL(hcrc->Init.DefaultPolynomialUse));
if(hcrc->Init.DefaultPolynomialUse == DEFAULT_POLYNOMIAL_ENABLE)
{
/* initialize IP with default generating polynomial */
WRITE_REG(hcrc->Instance->POL, DEFAULT_CRC32_POLY);
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, CRC_POLYLENGTH_32B);
}
else
{
/* initialize CRC IP with generating polynomial defined by user */
if(HAL_CRCEx_Polynomial_Set(hcrc, hcrc->Init.GeneratingPolynomial, hcrc->Init.CRCLength) != HAL_OK)
{
return HAL_ERROR;
}
}
/* check whether or not non-default CRC initial value has been
* picked up by user */
assert_param(IS_DEFAULT_INIT_VALUE(hcrc->Init.DefaultInitValueUse));
if(hcrc->Init.DefaultInitValueUse == DEFAULT_INIT_VALUE_ENABLE)
{
WRITE_REG(hcrc->Instance->INIT, DEFAULT_CRC_INITVALUE);
}
else
{
WRITE_REG(hcrc->Instance->INIT, hcrc->Init.InitValue);
}
/* set input data inversion mode */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(hcrc->Init.InputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, hcrc->Init.InputDataInversionMode);
/* set output data inversion mode */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(hcrc->Init.OutputDataInversionMode));
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, hcrc->Init.OutputDataInversionMode);
/* makes sure the input data format (bytes, halfwords or words stream)
* is properly specified by user */
assert_param(IS_CRC_INPUTDATA_FORMAT(hcrc->InputDataFormat));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitialize the CRC peripheral.
* @param hcrc: CRC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
{
/* Check the CRC handle allocation */
if(hcrc == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
/* Check the CRC peripheral state */
if(hcrc->State == HAL_CRC_STATE_BUSY)
{
return HAL_BUSY;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC calculation unit */
__HAL_CRC_DR_RESET(hcrc);
/* Reset IDR register content */
CLEAR_BIT(hcrc->Instance->IDR, CRC_IDR_IDR);
/* DeInit the low level hardware */
HAL_CRC_MspDeInit(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_RESET;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the CRC MSP.
* @param hcrc: CRC handle
* @retval None
*/
__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspInit can be implemented in the user file
*/
}
/**
* @brief DeInitialize the CRC MSP.
* @param hcrc: CRC handle
* @retval None
*/
__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcrc);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_CRC_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup HAL_CRC_Group2 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
using combination of the previous CRC value and the new one.
or
(+) Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
independently of the previous CRC value.
@endverbatim
* @{
*/
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with the previously computed CRC as initialization value.
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0; /* CRC input data buffer index */
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */
__HAL_LOCK(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter Data to the CRC calculator */
for(index = 0; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return the CRC computed value */
return temp;
}
/**
* @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
* starting with hcrc->Instance->INIT as initialization value.
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer, exact input data format is
* provided by hcrc->InputDataFormat.
* @param BufferLength: input data buffer length (number of bytes if pBuffer
* type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
* number of words if pBuffer type is * uint32_t).
* @note By default, the API expects a uint32_t pointer as input buffer parameter.
* Input buffer pointers with other types simply need to be cast in uint32_t
* and the API will internally adjust its input data processing based on the
* handle field hcrc->InputDataFormat.
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
{
uint32_t index = 0; /* CRC input data buffer index */
uint32_t temp = 0; /* CRC output (read from hcrc->Instance->DR register) */
/* Process locked */
__HAL_LOCK(hcrc);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* Reset CRC Calculation Unit (hcrc->Instance->INIT is
* written in hcrc->Instance->DR) */
__HAL_CRC_DR_RESET(hcrc);
switch (hcrc->InputDataFormat)
{
case CRC_INPUTDATA_FORMAT_WORDS:
/* Enter 32-bit input data to the CRC calculator */
for(index = 0; index < BufferLength; index++)
{
hcrc->Instance->DR = pBuffer[index];
}
temp = hcrc->Instance->DR;
break;
case CRC_INPUTDATA_FORMAT_BYTES:
/* Specific 8-bit input data handling */
temp = CRC_Handle_8(hcrc, (uint8_t*)pBuffer, BufferLength);
break;
case CRC_INPUTDATA_FORMAT_HALFWORDS:
/* Specific 16-bit input data handling */
temp = CRC_Handle_16(hcrc, (uint16_t*)pBuffer, BufferLength);
break;
default:
break;
}
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcrc);
/* Return the CRC computed value */
return temp;
}
/**
* @brief Enter 8-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer
* @param BufferLength: input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
{
uint32_t i = 0; /* input data buffer index */
/* Processing time optimization: 4 bytes are entered in a row with a single word write,
* last bytes must be carefully fed to the CRC calculator to ensure a correct type
* handling by the IP */
for(i = 0; i < (BufferLength/4); i++)
{
hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3]));
}
/* last bytes specific handling */
if((BufferLength%4) != 0)
{
if(BufferLength%4 == 1)
{
*(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
}
if(BufferLength%4 == 2)
{
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
}
if(BufferLength%4 == 3)
{
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
*(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
}
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @brief Enter 16-bit input data to the CRC calculator.
* Specific data handling to optimize processing time.
* @param hcrc: CRC handle
* @param pBuffer: pointer to the input data buffer
* @param BufferLength: input data buffer length
* @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
*/
static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
{
uint32_t i = 0; /* input data buffer index */
/* Processing time optimization: 2 HalfWords are entered in a row with a single word write,
* in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure
* a correct type handling by the IP */
for(i = 0; i < (BufferLength/2); i++)
{
hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1]));
}
if((BufferLength%2) != 0)
{
*(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
}
/* Return the CRC computed value */
return hcrc->Instance->DR;
}
/**
* @}
*/
/** @defgroup HAL_CRC_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
==============================================================================
##### Peripheral State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Return the CRC state.
* @param hcrc: CRC handle
* @retval HAL state
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
{
return hcrc->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_crc_ex.c
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/**
******************************************************************************
* @file stm32f7xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the CRC peripheral:
* + Initialization/de-initialization functions
*
@verbatim
==============================================================================
##### CRC specific features #####
==============================================================================
[..]
(#) Polynomial configuration.
(#) Input data reverse mode.
(#) Output data reverse mode.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup CRCEx
* @brief CRC Extended HAL module driver
* @{
*/
#ifdef HAL_CRC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions
* @{
*/
/** @addtogroup CRCEx_Exported_Functions_Group1
* @brief Extended CRC features functions
*
@verbatim
===============================================================================
##### CRC Extended features functions #####
===============================================================================
[..]
This subsection provides function allowing to:
(+) Set CRC polynomial if different from default one.
@endverbatim
* @{
*/
/**
* @brief Initializes the CRC polynomial if different from default one.
* @param hcrc: CRC handle
* @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long)
* This parameter is written in normal representation, e.g.
* for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021
* @param PolyLength: CRC polynomial length
* This parameter can be one of the following values:
* @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
* @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
* @arg CRC_POLYLENGTH_16B: 16-bit long CRC (generating polynomial of degree 16)
* @arg CRC_POLYLENGTH_32B: 32-bit long CRC (generating polynomial of degree 32)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength)
{
uint32_t msb = 31; /* polynomial degree is 32 at most, so msb is initialized to max value */
/* Check the parameters */
assert_param(IS_CRC_POL_LENGTH(PolyLength));
/* check polynomial definition vs polynomial size:
* polynomial length must be aligned with polynomial
* definition. HAL_ERROR is reported if Pol degree is
* larger than that indicated by PolyLength.
* Look for MSB position: msb will contain the degree of
* the second to the largest polynomial member. E.g., for
* X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */
while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0))
{
}
switch (PolyLength)
{
case CRC_POLYLENGTH_7B:
if (msb >= HAL_CRC_LENGTH_7B)
{
return HAL_ERROR;
}
break;
case CRC_POLYLENGTH_8B:
if (msb >= HAL_CRC_LENGTH_8B)
{
return HAL_ERROR;
}
break;
case CRC_POLYLENGTH_16B:
if (msb >= HAL_CRC_LENGTH_16B)
{
return HAL_ERROR;
}
break;
case CRC_POLYLENGTH_32B:
/* no polynomial definition vs. polynomial length issue possible */
break;
default:
break;
}
/* set generating polynomial */
WRITE_REG(hcrc->Instance->POL, Pol);
/* set generating polynomial size */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_POLYSIZE, PolyLength);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the Reverse Input data mode.
* @param hcrc: CRC handle
* @param InputReverseMode: Input Data inversion mode
* This parameter can be one of the following values:
* @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value)
* @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
* @arg CRC_INPUTDATA_INVERSION_HALFWORD: HalfWord-wise bit reversal
* @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set input data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_IN, InputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the Reverse Output data mode.
* @param hcrc: CRC handle
* @param OutputReverseMode: Output Data inversion mode
* This parameter can be one of the following values:
* @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
* @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode)
{
/* Check the parameters */
assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode));
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_BUSY;
/* set output data inversion mode */
MODIFY_REG(hcrc->Instance->CR, CRC_CR_REV_OUT, OutputReverseMode);
/* Change CRC peripheral state */
hcrc->State = HAL_CRC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_CRC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_dac.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Errors functions
*
*
@verbatim
==============================================================================
##### DAC Peripheral features #####
==============================================================================
[..]
*** DAC Channels ***
====================
[..]
The device integrates two 12-bit Digital Analog Converters that can
be used independently or simultaneously (dual mode):
(#) DAC channel1 with DAC_OUT1 (PA4) as output
(#) DAC channel2 with DAC_OUT2 (PA5) as output
*** DAC Triggers ***
====================
[..]
Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
[..]
Digital to Analog conversion can be triggered by:
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_TRIGGER_EXT_IT9.
The used pin (GPIOx_Pin9) must be configured in input mode.
(#) Timers TRGO: TIM2, TIM4, TIM5, TIM6, TIM7 and TIM8
(DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T4_TRGO...)
(#) Software using DAC_TRIGGER_SOFTWARE
*** DAC Buffer mode feature ***
===============================
[..]
Each DAC channel integrates an output buffer that can be used to
reduce the output impedance, and to drive external loads directly
without having to add an external operational amplifier.
To enable, the output buffer use
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
[..]
(@) Refer to the device datasheet for more details about output
impedance value with and without output buffer.
*** DAC wave generation feature ***
===================================
[..]
Both DAC channels can be used to generate
(#) Noise wave using HAL_DACEx_NoiseWaveGenerate()
(#) Triangle wave using HAL_DACEx_TriangleWaveGenerate()
*** DAC data format ***
=======================
[..]
The DAC data format can be:
(#) 8-bit right alignment using DAC_ALIGN_8B_R
(#) 12-bit left alignment using DAC_ALIGN_12B_L
(#) 12-bit right alignment using DAC_ALIGN_12B_R
*** DAC data value to voltage correspondence ***
================================================
[..]
The analog output voltage on each DAC channel pin is determined
by the following equation:
DAC_OUTx = VREF+ * DOR / 4095
with DOR is the Data Output Register
VEF+ is the input voltage reference (refer to the device datasheet)
e.g. To set DAC_OUT1 to 0.7V, use
Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
*** DMA requests ***
=====================
[..]
A DMA1 request can be generated when an external trigger (but not
a software trigger) occurs if DMA1 requests are enabled using
HAL_DAC_Start_DMA()
[..]
DMA1 requests are mapped as following:
(#) DAC channel1 : mapped on DMA1 Stream5 channel7 which must be
already configured
(#) DAC channel2 : mapped on DMA1 Stream6 channel7 which must be
already configured
-@- For Dual mode and specific signal (Triangle and noise) generation please
refer to Extension Features Driver description
##### How to use this driver #####
==============================================================================
[..]
(+) DAC APB clock must be enabled to get write access to DAC
registers using HAL_DAC_Init()
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
(+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
(+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
*** Polling mode IO operation ***
=================================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start()
(+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
(+) Stop the DAC peripheral using HAL_DAC_Stop()
*** DMA mode IO operation ***
==============================
[..]
(+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
of data to be transferred at each end of conversion
(+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()
function is executed and user can add his own code by customization of function pointer
HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
(+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
(+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
*** DAC HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DAC HAL driver.
(+) __HAL_DAC_ENABLE : Enable the DAC peripheral
(+) __HAL_DAC_DISABLE : Disable the DAC peripheral
(+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
[..]
(@) You can refer to the DAC HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup DAC DAC
* @brief DAC driver modules
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup DAC_Private_Functions
* @{
*/
/* Private function prototypes -----------------------------------------------*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DAC_Exported_Functions DAC Exported Functions
* @{
*/
/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DAC.
(+) De-initialize the DAC.
@endverbatim
* @{
*/
/**
* @brief Initializes the DAC peripheral according to the specified parameters
* in the DAC_InitStruct.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
{
/* Check DAC handle */
if(hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if(hdac->State == HAL_DAC_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Deinitializes the DAC peripheral registers to their default reset values.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
{
/* Check DAC handle */
if(hdac == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* DeInit the low level hardware */
HAL_DAC_MspDeInit(hdac);
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
/* Change DAC state */
hdac->State = HAL_DAC_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the DAC MSP.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the DAC MSP.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
@endverbatim
* @{
*/
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
uint32_t tmp1 = 0, tmp2 = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
if(Channel == DAC_CHANNEL_1)
{
tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
/* Check if software trigger enabled */
if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1))
{
/* Enable the selected DAC software conversion */
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1;
}
}
else
{
tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;
/* Check if software trigger enabled */
if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
{
/* Enable the selected DAC software conversion*/
hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG2;
}
}
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables DAC and starts conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param pData: The destination peripheral Buffer address.
* @param Length: The length of data to be transferred from memory to DAC peripheral
* @param Alignment: Specifies the data alignment for DAC channel.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
if(Channel == DAC_CHANNEL_1)
{
/* Set the DMA transfer complete callback for channel1 */
hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
/* Set the DMA half transfer complete callback for channel1 */
hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
/* Set the DMA error callback for channel1 */
hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
/* Enable the selected DAC channel1 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN1;
/* Case of use of channel 1 */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
break;
case DAC_ALIGN_8B_R:
/* Get DHR8R1 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
break;
default:
break;
}
}
else
{
/* Set the DMA transfer complete callback for channel2 */
hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
/* Set the DMA half transfer complete callback for channel2 */
hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
/* Set the DMA error callback for channel2 */
hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
/* Enable the selected DAC channel2 DMA request */
hdac->Instance->CR |= DAC_CR_DMAEN2;
/* Case of use of channel 2 */
switch(Alignment)
{
case DAC_ALIGN_12B_R:
/* Get DHR12R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
break;
case DAC_ALIGN_12B_L:
/* Get DHR12L2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
break;
case DAC_ALIGN_8B_R:
/* Get DHR8R2 address */
tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
break;
default:
break;
}
}
/* Enable the DMA Stream */
if(Channel == DAC_CHANNEL_1)
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
}
else
{
/* Enable the DAC DMA underrun interrupt */
__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
}
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
/* Process Unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disables DAC and stop conversion of channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Disable the selected DAC channel DMA request */
hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
/* Disable the Peripheral */
__HAL_DAC_DISABLE(hdac, Channel);
/* Disable the DMA Channel */
/* Channel1 is used */
if(Channel == DAC_CHANNEL_1)
{
status = HAL_DMA_Abort(hdac->DMA_Handle1);
}
else /* Channel2 is used for */
{
status = HAL_DMA_Abort(hdac->DMA_Handle2);
}
/* Check if DMA Channel effectively disabled */
if(status != HAL_OK)
{
/* Update DAC state machine to error */
hdac->State = HAL_DAC_STATE_ERROR;
}
else
{
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
}
/* Return function status */
return status;
}
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
/* Returns the DAC channel data output register value */
if(Channel == DAC_CHANNEL_1)
{
return hdac->Instance->DOR1;
}
else
{
return hdac->Instance->DOR2;
}
}
/**
* @brief Handles DAC interrupt request
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
{
/* Check underrun channel 1 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
/* Set DAC error code to channel1 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN1;
/* Error callback */
HAL_DAC_DMAUnderrunCallbackCh1(hdac);
}
/* Check underrun channel 2 flag */
if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
{
/* Change DAC state to error state */
hdac->State = HAL_DAC_STATE_ERROR;
/* Set DAC error code to channel2 DMA underrun error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
/* Clear the underrun flag */
__HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
/* Disable the selected DAC channel1 DMA request */
hdac->Instance->CR &= ~DAC_CR_DMAEN2;
/* Error callback */
HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
}
}
/**
* @brief Conversion complete callback in non blocking mode for Channel1
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallback could be implemented in the user file
*/
}
/**
* @brief Conversion half DMA transfer callback in non blocking mode for Channel1
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief Error DAC callback for Channel1.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
*/
}
/**
* @brief DMA underrun DAC callback for channel1.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
==============================================================================
##### Peripheral Control functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Configure channels.
(+) Set the specified data holding register value for DAC channel.
@endverbatim
* @{
*/
/**
* @brief Configures the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param sConfig: DAC configuration structure.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
{
uint32_t tmpreg1 = 0, tmpreg2 = 0;
/* Check the DAC parameters */
assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
assert_param(IS_DAC_CHANNEL(Channel));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
/* Configure for the selected DAC channel: buffer output, trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
/* Set BOFFx bit according to DAC_OutputBuffer value */
tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << Channel;
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
/* Disable wave generation */
hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the specified data holding register value for DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Alignment: Specifies the data alignment.
* This parameter can be one of the following values:
* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data: Data to be loaded in the selected data holding register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
__IO uint32_t tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data));
tmp = (uint32_t)hdac->Instance;
if(Channel == DAC_CHANNEL_1)
{
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
}
/* Set the DAC channel1 selected data holding register */
*(__IO uint32_t *) tmp = Data;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
* @brief Peripheral State and Errors functions
*
@verbatim
==============================================================================
##### Peripheral State and Errors functions #####
==============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DAC state.
(+) Check the DAC Errors.
@endverbatim
* @{
*/
/**
* @brief return the DAC state
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL state
*/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
{
/* Return DAC state */
return hdac->State;
}
/**
* @brief Return the DAC error code
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval DAC Error Code
*/
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
{
return hdac->ErrorCode;
}
/**
* @}
*/
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
HAL_DAC_ConvCpltCallbackCh1(hdac);
hdac->State= HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
}
/**
* @brief DMA error callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
HAL_DAC_ErrorCallbackCh1(hdac);
hdac->State= HAL_DAC_STATE_READY;
}
/**
* @}
*/
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dac_ex.c
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/**
******************************************************************************
* @file stm32f7xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
* + Extended features functions
*
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
(+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
(+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup DACEx DACEx
* @brief DAC driver modules
* @{
*/
#ifdef HAL_DAC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Functions DAC Exported Functions
* @{
*/
/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
==============================================================================
##### Extended features functions #####
==============================================================================
[..] This section provides functions allowing to:
(+) Start conversion.
(+) Stop conversion.
(+) Start conversion and enable DMA transfer.
(+) Stop conversion and disable DMA transfer.
(+) Get result of conversion.
(+) Get result of dual mode conversion.
@endverbatim
* @{
*/
/**
* @brief Returns the last data output value of the selected DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval The selected DAC channel data output value.
*/
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
{
uint32_t tmp = 0;
tmp |= hdac->Instance->DOR1;
tmp |= hdac->Instance->DOR2 << 16;
/* Returns the DAC channel data output register value */
return tmp;
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude: Select max triangle amplitude.
* This parameter can be one of the following values:
* @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
* @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
* @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
* @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
* @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
* @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
* @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
* @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
* @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
* @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
* @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
* @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Enables or disables the selected DAC channel wave generation.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Channel: The selected DAC channel.
* This parameter can be one of the following values:
* @arg DAC_CHANNEL_1: DAC Channel1 selected
* @arg DAC_CHANNEL_2: DAC Channel2 selected
* @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
* This parameter can be one of the following values:
* @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
* @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
* @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
{
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(Channel));
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
/* Process locked */
__HAL_LOCK(hdac);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
/* Enable the selected wave generation for the selected DAC channel */
MODIFY_REG(hdac->Instance->CR, (DAC_CR_WAVE1 | DAC_CR_MAMP1) << Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hdac);
/* Return function status */
return HAL_OK;
}
/**
* @brief Set the specified data holding register value for dual DAC channel.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @param Alignment: Specifies the data alignment for dual channel DAC.
* This parameter can be one of the following values:
* DAC_ALIGN_8B_R: 8bit right data alignment selected
* DAC_ALIGN_12B_L: 12bit left data alignment selected
* DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
* @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
* @note In dual mode, a unique register access is required to write in both
* DAC channels at the same time.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
{
uint32_t data = 0, tmp = 0;
/* Check the parameters */
assert_param(IS_DAC_ALIGN(Alignment));
assert_param(IS_DAC_DATA(Data1));
assert_param(IS_DAC_DATA(Data2));
/* Calculate and set dual DAC data holding register value */
if (Alignment == DAC_ALIGN_8B_R)
{
data = ((uint32_t)Data2 << 8) | Data1;
}
else
{
data = ((uint32_t)Data2 << 16) | Data1;
}
tmp = (uint32_t)hdac->Instance;
tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
/* Set the dual DAC selected data holding register */
*(__IO uint32_t *)tmp = data;
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @brief Conversion complete callback in non blocking mode for Channel2
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DAC_ConvCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Conversion half DMA transfer callback in non blocking mode for Channel2
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief Error DAC callback for Channel2.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief DMA underrun DAC callback for channel2.
* @param hdac: pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval None
*/
__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdac);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
*/
}
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
HAL_DACEx_ConvCpltCallbackCh2(hdac);
hdac->State= HAL_DAC_STATE_READY;
}
/**
* @brief DMA half transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Conversion complete callback */
HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
}
/**
* @brief DMA error callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
{
DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
/* Set DAC error code to DMA error */
hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
HAL_DACEx_ErrorCallbackCh2(hdac);
hdac->State= HAL_DAC_STATE_READY;
}
/**
* @}
*/
#endif /* HAL_DAC_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_dcmi.c
Executable
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/**
******************************************************************************
* @file stm32f7xx_hal_dcmi.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
* + Peripheral State and Error functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The sequence below describes how to use this driver to capture image
from a camera module connected to the DCMI Interface.
This sequence does not take into account the configuration of the
camera module, which should be made before to configure and enable
the DCMI to capture images.
(#) Program the required configuration through following parameters:
horizontal and vertical polarity, pixel clock polarity, Capture Rate,
Synchronization Mode, code of the frame delimiter and data width
using HAL_DCMI_Init() function.
(#) Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
register to the destination memory buffer.
(#) Program the required configuration through following parameters:
DCMI mode, destination memory Buffer address and the data length
and enable capture using HAL_DCMI_Start_DMA() function.
(#) Optionally, configure and Enable the CROP feature to select a rectangular
window from the received image using HAL_DCMI_ConfigCrop()
and HAL_DCMI_EnableCROP() functions
(#) The capture can be stopped using HAL_DCMI_Stop() function.
(#) To control DCMI state you can use the function HAL_DCMI_GetState().
*** DCMI HAL driver macros list ***
=============================================
[..]
Below the list of most used macros in DCMI HAL driver.
(+) __HAL_DCMI_ENABLE: Enable the DCMI peripheral.
(+) __HAL_DCMI_DISABLE: Disable the DCMI peripheral.
(+) __HAL_DCMI_GET_FLAG: Get the DCMI pending flags.
(+) __HAL_DCMI_CLEAR_FLAG: Clear the DCMI pending flags.
(+) __HAL_DCMI_ENABLE_IT: Enable the specified DCMI interrupts.
(+) __HAL_DCMI_DISABLE_IT: Disable the specified DCMI interrupts.
(+) __HAL_DCMI_GET_IT_SOURCE: Check whether the specified DCMI interrupt has occurred or not.
[..]
(@) You can refer to the DCMI HAL driver header file for more useful macros
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup DCMI DCMI
* @brief DCMI HAL module driver
* @{
*/
#ifdef HAL_DCMI_MODULE_ENABLED
#if defined (DCMI)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */
#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */
#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
/* Exported functions --------------------------------------------------------*/
/** @defgroup DCMI_Exported_Functions DCMI Exported Functions
* @{
*/
/** @defgroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DCMI
(+) De-initialize the DCMI
@endverbatim
* @{
*/
/**
* @brief Initializes the DCMI according to the specified
* parameters in the DCMI_InitTypeDef and create the associated handle.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
if(hdcmi == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
/* Init the low level hardware */
HAL_DCMI_MspInit(hdcmi);
}
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
DCMI_CR_LSM | DCMI_CR_OELS);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
hdcmi->Init.LineSelectStart);
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
}
/* Enable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
return HAL_OK;
}
/**
* @brief Deinitializes the DCMI peripheral registers to their default reset
* values.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi)
{
/* DeInit the low level hardware */
HAL_DCMI_MspDeInit(hdcmi);
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @brief Initializes the DCMI MSP.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspInit could be implemented in the user file
*/
}
/**
* @brief DeInitializes the DCMI MSP.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_MspDeInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DCMI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure destination address and data length and
Enables DCMI DMA request and enables DCMI capture
(+) Stop the DCMI capture.
(+) Handles DCMI interrupt request.
@endverbatim
* @{
*/
/**
* @brief Enables DCMI DMA request and enables DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
* @param pData: The destination memory Buffer address (LCD Frame buffer).
* @param Length: The length of capture to be transferred.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
{
/* Initialize the second memory address */
uint32_t SecondMemAddress = 0;
/* Check function parameters */
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Enable DCMI by setting DCMIEN bit */
__HAL_DCMI_ENABLE(hdcmi);
/* Configure the DCMI Mode */
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
/* Set the DMA memory0 conversion complete callback */
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
/* Set the DMA error callback */
hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
/* Set the dma abort callback */
hdcmi->DMA_Handle->XferAbortCallback = NULL;
/* Reset transfer counters value */
hdcmi->XferCount = 0;
hdcmi->XferTransferNumber = 0;
if(Length <= 0xFFFF)
{
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, Length);
}
else /* DCMI_DOUBLE_BUFFER Mode */
{
/* Set the DMA memory1 conversion complete callback */
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
/* Initialize transfer parameters */
hdcmi->XferCount = 1;
hdcmi->XferSize = Length;
hdcmi->pBuffPtr = pData;
/* Get the number of buffer */
while(hdcmi->XferSize > 0xFFFF)
{
hdcmi->XferSize = (hdcmi->XferSize/2);
hdcmi->XferCount = hdcmi->XferCount*2;
}
/* Update DCMI counter and transfer number*/
hdcmi->XferCount = (hdcmi->XferCount - 2);
hdcmi->XferTransferNumber = hdcmi->XferCount;
/* Update second memory address */
SecondMemAddress = (uint32_t)(pData + (4*hdcmi->XferSize));
/* Start DMA multi buffer transfer */
HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
}
/* Enable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return HAL_OK;
}
/**
* @brief Disable DCMI DMA request and Disable DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
{
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable Capture */
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
/* Check if the DCMI capture effectively disabled */
do
{
if (count-- == 0)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
status = HAL_TIMEOUT;
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
/* Disable the DMA */
HAL_DMA_Abort(hdcmi->DMA_Handle);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_NONE;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return status;
}
/**
* @brief Suspend DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
{
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_BUSY)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
/* Disable Capture */
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
/* Check if the DCMI capture effectively disabled */
do
{
if (count-- == 0)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
status = HAL_TIMEOUT;
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return status;
}
/**
* @brief Resume DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
{
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return HAL_OK;
}
/**
* @brief Handles DCMI interrupt request.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI.
* @retval None
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
{
uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
/* Synchronization error interrupt management *******************************/
if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
{
/* Clear the Synchronization error flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Set the synchronization error callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Overflow interrupt management ********************************************/
if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
{
/* Clear the Overflow flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Set the overflow callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Line Interrupt management ************************************************/
if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
{
/* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Line interrupt Callback */
HAL_DCMI_LineEventCallback(hdcmi);
}
/* VSYNC interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
{
/* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* VSYNC Callback */
HAL_DCMI_VsyncEventCallback(hdcmi);
}
/* FRAME interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
{
/* When snapshot mode, disable Vsync, Error and Overrun interrupts */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
/* Disable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
}
/* Disable the Frame interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
/* Clear the End of Frame flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
/* Frame Callback */
HAL_DCMI_FrameEventCallback(hdcmi);
}
}
/**
* @brief Error DCMI callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_ErrorCallback could be implemented in the user file
*/
}
/**
* @brief Line Event callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_LineEventCallback could be implemented in the user file
*/
}
/**
* @brief VSYNC Event callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_VsyncEventCallback could be implemented in the user file
*/
}
/**
* @brief Frame Event callback.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
__weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdcmi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DCMI_FrameEventCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup DCMI_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
(+) Enable/Disable the CROP feature.
(+) Set embedded synchronization delimiters unmasks.
@endverbatim
* @{
*/
/**
* @brief Configure the DCMI CROP coordinate.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @param YSize: DCMI Line number
* @param XSize: DCMI Pixel per line
* @param X0: DCMI window X offset
* @param Y0: DCMI window Y offset
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Check the parameters */
assert_param(IS_DCMI_WINDOW_COORDINATE(X0));
assert_param(IS_DCMI_WINDOW_HEIGHT(Y0));
assert_param(IS_DCMI_WINDOW_COORDINATE(XSize));
assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
/* Configure CROP */
hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @brief Disable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable DCMI Crop feature */
hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @brief Enable the Crop feature.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Enable DCMI Crop feature */
hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup DCMI_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DCMI state.
(+) Get the specific DCMI error flag.
@endverbatim
* @{
*/
/**
* @brief Return the DCMI state
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL state
*/
HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->State;
}
/**
* @brief Return the DCMI error code
* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval DCMI Error Code
*/
uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
{
return hdcmi->ErrorCode;
}
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Functions DCMI Private Functions
* @{
*/
/**
* @brief DMA conversion complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0;
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if(hdcmi->XferCount != 0)
{
/* Update memory 0 address location */
tmp = ((hdcmi->DMA_Handle->Instance->CR) & DMA_SxCR_CT);
if(((hdcmi->XferCount % 2) == 0) && (tmp != 0))
{
tmp = hdcmi->DMA_Handle->Instance->M0AR;
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY0);
hdcmi->XferCount--;
}
/* Update memory 1 address location */
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
{
tmp = hdcmi->DMA_Handle->Instance->M1AR;
HAL_DMAEx_ChangeMemory(hdcmi->DMA_Handle, (tmp + (8*hdcmi->XferSize)), MEMORY1);
hdcmi->XferCount--;
}
}
/* Update memory 0 address location */
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) != 0)
{
hdcmi->DMA_Handle->Instance->M0AR = hdcmi->pBuffPtr;
}
/* Update memory 1 address location */
else if((hdcmi->DMA_Handle->Instance->CR & DMA_SxCR_CT) == 0)
{
tmp = hdcmi->pBuffPtr;
hdcmi->DMA_Handle->Instance->M1AR = (tmp + (4*hdcmi->XferSize));
hdcmi->XferCount = hdcmi->XferTransferNumber;
}
/* Check if the frame is transferred */
if(hdcmi->XferCount == hdcmi->XferTransferNumber)
{
/* Enable the Frame interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
/* When snapshot mode, set dcmi state to ready */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
hdcmi->State= HAL_DCMI_STATE_READY;
}
}
}
/**
* @brief DMA error callback
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
{
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
{
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Set DCMI Error Code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
}
/* DCMI error Callback */
HAL_DCMI_ErrorCallback(hdcmi);
}
/**
* @}
*/
/**
* @}
*/
#endif /* DCMI */
#endif /* HAL_DCMI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief Empty file; This file is no longer used to handle the Black&White
* feature. Its content is now moved to common files
* (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7
* family. It's just kept for compatibility reasons.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_dma_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The DMA Extension HAL driver can be used as follows:
(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup DMAEx DMAEx
* @brief DMA Extended HAL module driver
* @{
*/
#ifdef HAL_DMA_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private Constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @}
*/
/* Exported functions ---------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/** @addtogroup DMAEx_Exported_Functions_Group1
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer
(+) Configure the source, destination address and data length and
Start MultiBuffer DMA transfer with interrupt
(+) Change on the fly the memory0 or memory1 address.
@endverbatim
* @{
*/
/**
* @brief Starts the multi_buffer DMA Transfer.
* @param hdma : pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
}
else
{
/* Process Locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Enable the double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Return error status */
status = HAL_BUSY;
}
}
return status;
}
/**
* @brief Starts the multi_buffer DMA Transfer with interrupt enabled.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Enable the Double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
/* Enable Common interrupts*/
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
hdma->Instance->FCR |= DMA_IT_FE;
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
hdma->Instance->CR |= DMA_IT_HT;
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdma);
/* Return error status */
status = HAL_BUSY;
}
return status;
}
/**
* @brief Change the memory0 or memory1 address on the fly.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param Address: The new address
* @param memory: the memory to be changed, This parameter can be one of
* the following values:
* MEMORY0 /
* MEMORY1
* @note The MEMORY0 address can be changed only when the current transfer use
* MEMORY1 and the MEMORY1 address can be changed only when the current
* transfer use MEMORY0.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
{
if(memory == MEMORY0)
{
/* change the memory0 address */
hdma->Instance->M0AR = Address;
}
else
{
/* change the memory1 address */
hdma->Instance->M1AR = Address;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
/**
* @brief Set the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
hdma->Instance->PAR = DstAddress;
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
hdma->Instance->PAR = SrcAddress;
/* Configure DMA Stream destination address */
hdma->Instance->M0AR = DstAddress;
}
}
/**
* @}
*/
#endif /* HAL_DMA_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
* + Program operations functions
* + Memory Control functions
* + Peripheral Errors functions
*
@verbatim
==============================================================================
##### FLASH peripheral features #####
==============================================================================
[..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses
to the Flash memory. It implements the erase and program Flash memory operations
and the read and write protection mechanisms.
[..] The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines.
[..] The FLASH main features are:
(+) Flash memory read operations
(+) Flash memory program/erase operations
(+) Read / write protections
(+) Prefetch on I-Code
(+) 64 cache lines of 128 bits on I-Code
(+) 8 cache lines of 128 bits on D-Code
##### How to use this driver #####
==============================================================================
[..]
This driver provides functions and macros to configure and program the FLASH
memory of all STM32F7xx devices.
(#) FLASH Memory IO Programming functions:
(++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
HAL_FLASH_Lock() functions
(++) Program functions: byte, half word, word and double word
(++) There Two modes of programming :
(+++) Polling mode using HAL_FLASH_Program() function
(+++) Interrupt mode using HAL_FLASH_Program_IT() function
(#) Interrupts and flags management functions :
(++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
(++) Wait for last FLASH operation according to its status
(++) Get error flag status by calling HAL_SetErrorCode()
[..]
In addition to these functions, this driver includes a set of macros allowing
to handle the following operations:
(+) Set the latency
(+) Enable/Disable the prefetch buffer
(+) Enable/Disable the Instruction cache and the Data cache
(+) Reset the Instruction cache and the Data cache
(+) Enable/Disable the FLASH interrupts
(+) Monitor the FLASH flags status
[..]
(@) For any Flash memory program operation (erase or program), the CPU clock frequency
(HCLK) must be at least 1MHz.
(@) The contents of the Flash memory are not guaranteed if a device reset occurs during
a Flash memory operation.
(@) Any attempt to read the Flash memory while it is being written or erased, causes the
bus to stall. Read operations are processed correctly once the program operation has
completed. This means that code or data fetches cannot be performed while a write/erase
operation is ongoing.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup FLASH FLASH
* @brief FLASH HAL module driver
* @{
*/
#ifdef HAL_FLASH_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define SECTOR_MASK ((uint32_t)0xFFFFFF07U)
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @addtogroup FLASH_Private_Variables
* @{
*/
/* Variable used for Erase sectors under interruption */
FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
/* Program operations */
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
static void FLASH_Program_Word(uint32_t Address, uint32_t Data);
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data);
static void FLASH_SetErrorCode(void);
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
* @{
*/
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
* @brief Programming operation functions
*
@verbatim
===============================================================================
##### Programming operation functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to manage the FLASH
program operations.
@endverbatim
* @{
*/
/**
* @brief Program byte, halfword, word or double word at a specified address
* @param TypeProgram: Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_ERROR;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
switch(TypeProgram)
{
case FLASH_TYPEPROGRAM_BYTE :
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
break;
}
case FLASH_TYPEPROGRAM_HALFWORD :
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
break;
}
case FLASH_TYPEPROGRAM_WORD :
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
break;
}
case FLASH_TYPEPROGRAM_DOUBLEWORD :
{
/*Program double word (64-bit) at a specified address.*/
FLASH_Program_DoubleWord(Address, Data);
break;
}
default :
break;
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the program operation is completed, disable the PG Bit */
FLASH->CR &= (~FLASH_CR_PG);
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
return status;
}
/**
* @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.
* @param TypeProgram: Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(&pFlash);
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Enable End of FLASH Operation interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
/* Enable Error source interrupt */
__HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
/* Clear pending flags (if any) */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\
FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_ERSERR);
pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
pFlash.Address = Address;
switch(TypeProgram)
{
case FLASH_TYPEPROGRAM_BYTE :
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
break;
}
case FLASH_TYPEPROGRAM_HALFWORD :
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
break;
}
case FLASH_TYPEPROGRAM_WORD :
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
break;
}
case FLASH_TYPEPROGRAM_DOUBLEWORD :
{
/*Program double word (64-bit) at a specified address.*/
FLASH_Program_DoubleWord(Address, Data);
break;
}
default :
break;
}
return status;
}
/**
* @brief This function handles FLASH interrupt request.
* @retval None
*/
void HAL_FLASH_IRQHandler(void)
{
uint32_t temp = 0;
/* If the program operation is completed, disable the PG Bit */
FLASH->CR &= (~FLASH_CR_PG);
/* If the erase operation is completed, disable the SER Bit */
FLASH->CR &= (~FLASH_CR_SER);
FLASH->CR &= SECTOR_MASK;
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_MER_BIT);
/* Check FLASH End of Operation flag */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
switch (pFlash.ProcedureOnGoing)
{
case FLASH_PROC_SECTERASE :
{
/* Nb of sector to erased can be decreased */
pFlash.NbSectorsToErase--;
/* Check if there are still sectors to erase */
if(pFlash.NbSectorsToErase != 0)
{
temp = pFlash.Sector;
/* Indicate user which sector has been erased */
HAL_FLASH_EndOfOperationCallback(temp);
/* Increment sector number */
temp = ++pFlash.Sector;
FLASH_Erase_Sector(temp, pFlash.VoltageForErase);
}
else
{
/* No more sectors to Erase, user callback can be called.*/
/* Reset Sector and stop Erase sectors procedure */
pFlash.Sector = temp = 0xFFFFFFFFU;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(temp);
/* Sector Erase procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
break;
}
case FLASH_PROC_MASSERASE :
{
/* MassErase ended. Return the selected bank : in this product we don't have Banks */
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(0);
/* MAss Erase procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
break;
}
case FLASH_PROC_PROGRAM :
{
/*Program ended. Return the selected address*/
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(pFlash.Address);
/* Programming procedure is completed */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
break;
}
default :
break;
}
}
/* Check FLASH operation error flags */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
{
switch (pFlash.ProcedureOnGoing)
{
case FLASH_PROC_SECTERASE :
{
/* return the faulty sector */
temp = pFlash.Sector;
pFlash.Sector = 0xFFFFFFFFU;
break;
}
case FLASH_PROC_MASSERASE :
{
/* No return in case of Mass Erase */
temp = 0;
break;
}
case FLASH_PROC_PROGRAM :
{
/*return the faulty address*/
temp = pFlash.Address;
break;
}
default :
break;
}
/*Save the Error code*/
FLASH_SetErrorCode();
/* FLASH error interrupt user callback */
HAL_FLASH_OperationErrorCallback(temp);
/*Stop the procedure ongoing */
pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
}
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
{
/* Disable End of FLASH Operation interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
/* Disable Error source interrupt */
__HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
}
}
/**
* @brief FLASH end of operation interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
* - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
* all the selected sectors have been erased)
* - Program : Address which was selected for data program
* - Mass Erase : No return value expected
* @retval None
*/
__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
*/
}
/**
* @brief FLASH operation error interrupt callback
* @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
* - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
* all the selected sectors have been erased)
* - Program : Address which was selected for data program
* - Mass Erase : No return value expected
* @retval None
*/
__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(ReturnValue);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_FLASH_OperationErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
* @brief management functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the FLASH
memory operations.
@endverbatim
* @{
*/
/**
* @brief Unlock the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
if((FLASH->CR & FLASH_CR_LOCK) != RESET)
{
/* Authorize the FLASH Registers access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Locks the FLASH control register access
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Lock(void)
{
/* Set the LOCK Bit to lock the FLASH Registers access */
FLASH->CR |= FLASH_CR_LOCK;
return HAL_OK;
}
/**
* @brief Unlock the FLASH Option Control Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
{
if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
{
/* Authorizes the Option Byte register programming */
FLASH->OPTKEYR = FLASH_OPT_KEY1;
FLASH->OPTKEYR = FLASH_OPT_KEY2;
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @brief Lock the FLASH Option Control Registers access.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
return HAL_OK;
}
/**
* @brief Launch the option byte loading.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{
/* Set the OPTSTRT bit in OPTCR register */
FLASH->OPTCR |= FLASH_OPTCR_OPTSTRT;
/* Wait for last operation to be completed */
return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE));
}
/**
* @}
*/
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
* @brief Peripheral Errors functions
*
@verbatim
===============================================================================
##### Peripheral Errors functions #####
===============================================================================
[..]
This subsection permits to get in run-time Errors of the FLASH peripheral.
@endverbatim
* @{
*/
/**
* @brief Get the specific FLASH error flag.
* @retval FLASH_ErrorCode: The returned value can be:
* @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag
* @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag
* @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
* @arg FLASH_ERROR_WRP: FLASH Write protected error flag
* @arg FLASH_ERROR_OPERATION: FLASH operation Error flag
*/
uint32_t HAL_FLASH_GetError(void)
{
return pFlash.ErrorCode;
}
/**
* @}
*/
/**
* @brief Wait for a FLASH operation to complete.
* @param Timeout: maximum flash operationtimeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
uint32_t tickstart = 0;
/* Clear Error Code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
{
if(Timeout != HAL_MAX_DELAY)
{
if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
{
return HAL_TIMEOUT;
}
}
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ALL_ERRORS) != RESET)
{
/*Save the error code*/
FLASH_SetErrorCode();
return HAL_ERROR;
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
/* If there is an error flag set */
return HAL_OK;
}
/**
* @brief Program a double word (64-bit) at a specified address.
* @note This function must be used when the device voltage range is from
* 2.7V to 3.6V and an External Vpp is present.
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint64_t*)Address = Data;
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
}
/**
* @brief Program word (32-bit) at a specified address.
* @note This function must be used when the device voltage range is from
* 2.7V to 3.6V.
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_PSIZE_WORD;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint32_t*)Address = Data;
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
}
/**
* @brief Program a half-word (16-bit) at a specified address.
* @note This function must be used when the device voltage range is from
* 2.7V to 3.6V.
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint16_t*)Address = Data;
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
}
/**
* @brief Program byte (8-bit) at a specified address.
* @note This function must be used when the device voltage range is from
* 2.7V to 3.6V.
*
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
* @param Address: specifies the address to be programmed.
* @param Data: specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
{
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_PSIZE_BYTE;
FLASH->CR |= FLASH_CR_PG;
*(__IO uint8_t*)Address = Data;
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
}
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ERSERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_ERS;
}
#if defined (FLASH_OPTCR2_PCROP)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
}
#endif /* FLASH_OPTCR2_PCROP */
/* Clear error programming flags */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
}
/**
* @}
*/
#endif /* HAL_FLASH_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_gpio.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
*
@verbatim
==============================================================================
##### GPIO Peripheral features #####
==============================================================================
[..]
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
in several modes:
(+) Input mode
(+) Analog mode
(+) Output mode
(+) Alternate function mode
(+) External interrupt/event lines
[..]
During and just after reset, the alternate functions and external interrupt
lines are not active and the I/O ports are configured in input floating mode.
[..]
All GPIO pins have weak internal pull-up and pull-down resistors, which can be
activated or not.
[..]
In Output or Alternate mode, each IO can be configured on open-drain or push-pull
type and the IO speed can be selected depending on the VDD value.
[..]
All ports have external interrupt/event capability. To use external interrupt
lines, the port must be configured in input mode. All available GPIO pins are
connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
[..]
The external interrupt/event controller consists of up to 23 edge detectors
(16 lines are connected to GPIO) for generating event/interrupt requests (each
input line can be independently configured to select the type (interrupt or event)
and the corresponding trigger event (rising or falling or both). Each line can
also be masked independently.
##### How to use this driver #####
==============================================================================
[..]
(#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
(#) Configure the GPIO pin(s) using HAL_GPIO_Init().
(++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
(++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
structure.
(++) In case of Output or alternate function mode selection: the speed is
configured through "Speed" member from GPIO_InitTypeDef structure.
(++) In alternate mode is selection, the alternate function connected to the IO
is configured through "Alternate" member from GPIO_InitTypeDef structure.
(++) Analog mode is required when a pin is to be used as ADC channel
or DAC output.
(++) In case of external interrupt/event selection the "Mode" member from
GPIO_InitTypeDef structure select the type (interrupt or event) and
the corresponding trigger event (rising or falling or both).
(#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
HAL_NVIC_EnableIRQ().
(#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
(#) To set/reset the level of a pin configured in output mode use
HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
(#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
(#) During and just after reset, the alternate functions are not
active and the GPIO pins are configured in input floating mode (except JTAG
pins).
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
(PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
priority over the GPIO function.
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
The HSE has priority over the GPIO function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
#ifdef HAL_GPIO_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE ((uint32_t)0x00000003U)
#define EXTI_MODE ((uint32_t)0x10000000U)
#define GPIO_MODE_IT ((uint32_t)0x00010000U)
#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define RISING_EDGE ((uint32_t)0x00100000U)
#define FALLING_EDGE ((uint32_t)0x00200000U)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define GPIO_NUMBER ((uint32_t)16U)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to initialize and de-initialize the GPIOs
to be ready for use.
@endverbatim
* @{
*/
/**
* @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
uint32_t position = 0x00;
uint32_t ioposition = 0x00;
uint32_t iocurrent = 0x00;
uint32_t temp = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
if(iocurrent == ioposition)
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3];
temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
GPIOx->AFR[position >> 3] = temp;
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
temp &= ~(GPIO_MODER_MODER0 << (position * 2));
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
GPIOx->MODER = temp;
/* In case of Output or Alternate function mode selection */
if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
(GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
temp |= (GPIO_Init->Speed << (position * 2));
GPIOx->OSPEEDR = temp;
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
GPIOx->OTYPER = temp;
}
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
temp |= ((GPIO_Init->Pull) << (position * 2));
GPIOx->PUPDR = temp;
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
temp = SYSCFG->EXTICR[position >> 2];
temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03)));
SYSCFG->EXTICR[position >> 2] = temp;
/* Clear EXTI line configuration */
temp = EXTI->IMR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
{
temp |= iocurrent;
}
EXTI->IMR = temp;
temp = EXTI->EMR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
{
temp |= iocurrent;
}
EXTI->EMR = temp;
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
{
temp |= iocurrent;
}
EXTI->RTSR = temp;
temp = EXTI->FTSR;
temp &= ~((uint32_t)iocurrent);
if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
{
temp |= iocurrent;
}
EXTI->FTSR = temp;
}
}
}
}
/**
* @brief De-initializes the GPIOx peripheral registers to their default reset values.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
{
uint32_t position;
uint32_t ioposition = 0x00;
uint32_t iocurrent = 0x00;
uint32_t tmp = 0x00;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Configure the port pins */
for(position = 0; position < GPIO_NUMBER; position++)
{
/* Get the IO position */
ioposition = ((uint32_t)0x01) << position;
/* Get the current IO position */
iocurrent = (GPIO_Pin) & ioposition;
if(iocurrent == ioposition)
{
/*------------------------- GPIO Mode Configuration --------------------*/
/* Configure IO Direction in Input Floating Mode */
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2));
/* Configure the default Alternate Function in current IO */
GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
/* Configure the default value for IO Speed */
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
/* Configure the default value IO Output Type */
GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ;
/* Deactivate the Pull-up and Pull-down resistor for the current IO */
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2));
/*------------------------- EXTI Mode Configuration --------------------*/
tmp = SYSCFG->EXTICR[position >> 2];
tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))))
{
/* Configure the External Interrupt or event for the current IO */
tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
SYSCFG->EXTICR[position >> 2] &= ~tmp;
/* Clear EXTI line configuration */
EXTI->IMR &= ~((uint32_t)iocurrent);
EXTI->EMR &= ~((uint32_t)iocurrent);
/* Clear Rising Falling edge configuration */
EXTI->RTSR &= ~((uint32_t)iocurrent);
EXTI->FTSR &= ~((uint32_t)iocurrent);
}
}
}
}
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief GPIO Read and Write
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
@endverbatim
* @{
*/
/**
* @brief Reads the specified input port pin.
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
{
bitstatus = GPIO_PIN_SET;
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
}
/**
* @brief Sets or clears the selected data port bit.
*
* @note This function uses GPIOx_BSRR register to allow atomic read/modify
* accesses. In this way, there is no risk of an IRQ occurring between
* the read and the modify access.
*
* @param GPIOx: where x can be (A..K) to select the GPIO peripheral.
* @param GPIO_Pin: specifies the port bit to be written.
* This parameter can be one of GPIO_PIN_x where x can be (0..15).
* @param PinState: specifies the value to be written to the selected bit.
* This parameter can be one of the GPIO_PinState enum values:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
{
GPIOx->BSRR = GPIO_Pin;
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
}
}
/**
* @brief Toggles the specified GPIO pins.
* @param GPIOx: Where x can be (A..I) to select the GPIO peripheral.
* @param GPIO_Pin: Specifies the pins to be toggled.
* @retval None
*/
void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
GPIOx->ODR ^= GPIO_Pin;
}
/**
* @brief Locks GPIO Pins configuration registers.
* @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
* @note The configuration of the locked GPIO pins can no longer be modified
* until the next reset.
* @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family
* @param GPIO_Pin: specifies the port bit to be locked.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
* @retval None
*/
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
__IO uint32_t tmp = GPIO_LCKR_LCKK;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
/* Apply lock key write sequence */
tmp |= GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp;
/* Read LCKK bit*/
tmp = GPIOx->LCKR;
if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
{
return HAL_OK;
}
else
{
return HAL_ERROR;
}
}
/**
* @brief This function handles EXTI interrupt request.
* @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None
*/
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
{
/* EXTI line interrupt detected */
if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
{
__HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
HAL_GPIO_EXTI_Callback(GPIO_Pin);
}
}
/**
* @brief EXTI line detection callbacks.
* @param GPIO_Pin: Specifies the pins connected EXTI line
* @retval None
*/
__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(GPIO_Pin);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_GPIO_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
*
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32F7xx
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable Fast Mode Plus
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to:
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisableFastModePlus()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup I2CEx I2CEx
* @brief I2C Extended HAL module driver
* @{
*/
#ifdef HAL_I2C_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configure I2C Analog noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
{
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
/**
* @brief Configure I2C Digital noise filter.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
{
uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8U;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
}
#if defined(SYSCFG_PMC_I2C1_FMP)
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be enabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be enabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @note For I2C1, fast mode plus driving capability can be disabled on all selected
* I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
* on each one of the following pins PB6, PB7, PB8 and PB9.
* @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
* can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
* @note For all I2C2 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C2 parameter.
* @note For all I2C3 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C3 parameter.
* @note For all I2C4 pins fast mode plus driving capability can be disabled
* only by using I2C_FASTMODEPLUS_I2C4 parameter.
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
}
#endif /* SYSCFG_PMC_I2C1_FMP */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief IWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and Start functions
* + IO operation functions
*
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
##### How to use this driver #####
==============================================================================
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(++) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
IWDG_WINR.
(++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(++) wait for status flags to be reset
(++) Depending on window parameter:
(+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function withy exact time base.
(+++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Manage Window option.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart;
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Enable IWDG. LSI is turned on automaticaly */
__HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while(hiwdg->Instance->SR != RESET)
{
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* If window parameter is different than current value, modify window
register */
if(hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
even if window feature is disabled, Watchdog will be reloaded by writing
windows register */
hiwdg->Instance->WINR = hiwdg->Init.Window;
}
else
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_IWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_ltdc_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
#ifdef HAL_LTDC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
#if defined (STM32F769xx) || defined (STM32F779xx)
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarity is inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
return HAL_OK;
}
#endif /*STM32F769xx | STM32F779xx */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_LTCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mdios.c
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/**
******************************************************************************
* @file stm32f7xx_hal_mdios.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief MDIOS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the MDIOS Peripheral.
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The MDIOS HAL driver can be used as follows:
(#) Declare a MDIOS_HandleTypeDef handle structure.
(#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
(##) Enable the MDIOS interface clock.
(##) MDIOS pins configuration:
(+++) Enable clocks for the MDIOS GPIOs.
(+++) Configure the MDIOS pins as alternate function.
(##) NVIC configuration if you need to use interrupt process:
(+++) Configure the MDIOS interrupt priority.
(+++) Enable the NVIC MDIOS IRQ handle.
(#) Program the Port Address and the Preamble Check in the Init structure.
(#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.
(#) Perform direct slave read/write operations using the following APIs:
(##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
(##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
(#) Get the Master read/write operations flags using the following APIs:
(##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
(##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
(#) Clear the read/write flags using the following APIs:
(##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
(##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
(#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
the MDIOS will generate an interrupt in the following cases:
(##) a DINn register written by the Master
(##) a DOUTn register read by the Master
(##) an error occur
-@@- A callback is executed for each genereted interrupt, so the driver provides the following
HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
-@@- HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
and execute the previous callbacks
(#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
(##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
(GPIO, Clocks, NVIC configuration ...)
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup MDIOS MDIOS
* @brief HAL MDIOS module driver
* @{
*/
#ifdef HAL_MDIOS_MODULE_ENABLED
#if defined (MDIOS)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)
#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
* @{
*/
/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the MDIOS
(+) The following parameters can be configured:
(++) Port Address
(++) Preamble Check
@endverbatim
* @{
*/
/**
* @brief Initializes the MDIOS according to the specified parameters in
* the MDIOS_InitTypeDef and creates the associated handle .
* @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
* the configuration information for MDIOS module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
{
uint32_t tmpcr = 0;
/* Check the MDIOS handle allocation */
if(hmdios == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
/* Process Locked */
__HAL_LOCK(hmdios);
if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
/* Init the low level hardware */
HAL_MDIOS_MspInit(hmdios);
}
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
/* Get the MDIOS CR value */
tmpcr = hmdios->Instance->CR;
/* Clear PORT_ADDRESS, DPC and EN bits */
tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
/* Set MDIOS control parametrs and enable the peripheral */
tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\
(hmdios->Init.PreambleCheck) | \
(MDIOS_CR_EN));
/* Write the MDIOS CR */
hmdios->Instance->CR = tmpcr;
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hmdios);
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the MDIOS peripheral.
* @param hmdios: MDIOS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
{
/* Check the MDIOS handle allocation */
if(hmdios == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
/* Disable the Peripheral */
__HAL_MDIOS_DISABLE(hmdios);
/* DeInit the low level hardware */
HAL_MDIOS_MspDeInit(hmdios);
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hmdios);
/* Return function status */
return HAL_OK;
}
/**
* @brief MDIOS MSP Init
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspInit can be implemented in the user file
*/
}
/**
* @brief MDIOS MSP DeInit
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
* @brief MDIOS Read/Write functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the MDIOS
read and write operations.
(#) APIs that allow to the MDIOS to read/write from/to the
values of one of the DINn/DOUTn registers:
(+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
(+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
(#) APIs that provide if there are some Slave registres have been
read or written by the Master:
(+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
(+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
(#) APIs that Clear the read/write flags:
(+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
(+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()
(#) A set of Callbacks are provided:
(+) HAL_MDIOS_WriteCpltCallback()
(+) HAL_MDIOS_ReadCpltCallback()
(+) HAL_MDIOS_ErrorCallback()
@endverbatim
* @{
*/
/**
* @brief Writes to an MDIOS output register
* @param hmdios: mdios handle
* @param RegNum: MDIOS input register number
* @param Data: Data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Get the addr of output register to be written by the MDIOS */
tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum);
/* Write to DOUTn register */
*((uint32_t *)tmpreg) = Data;
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Reads an MDIOS input register
* @param hmdios: mdios handle
* @param RegNum: MDIOS input register number
* @param pData: pointer to Data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Get the addr of input register to be read by the MDIOS */
tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum);
/* Read DINn register */
*pData = (uint16_t)(*((uint32_t *)tmpreg));
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Gets Written registers by MDIO master
* @param hmdios: mdios handle
* @retval bit map of written registers addresses
*/
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
{
return hmdios->Instance->WRFR;
}
/**
* @brief Gets Read registers by MDIO master
* @param hmdios: mdios handle
* @retval bit map of read registers addresses
*/
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
{
return hmdios->Instance->RDFR;
}
/**
* @brief Clears Write registers flag
* @param hmdios: mdios handle
* @param RegNum: registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Clear write registers flags */
hmdios->Instance->CWRFR |= (RegNum);
/* Release Lock */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Clears Read register flag
* @param hmdios: mdios handle
* @param RegNum: registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Clear read registers flags */
hmdios->Instance->CRDFR |= (RegNum);
/* Release Lock */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Enables Events for MDIOS peripheral
* @param hmdios: mdios handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
{
/* Process Locked */
__HAL_LOCK(hmdios);
/* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
__HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief This function handles MDIOS interrupt request.
* @param hmdios: MDIOS handle
* @retval None
*/
void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
{
/* Write Register Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET)
{
/* Write register flag */
if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET)
{
/* Write callback function */
HAL_MDIOS_WriteCpltCallback(hmdios);
/* Clear write register flag */
HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
}
}
/* Read Register Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET)
{
/* Read register flag */
if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET)
{
/* Read callback function */
HAL_MDIOS_ReadCpltCallback(hmdios);
/* Clear read register flag */
HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
}
}
/* Error Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET)
{
/* All Errors Flag */
if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET)
{
/* Error Callback */
HAL_MDIOS_ErrorCallback(hmdios);
/* Clear errors flag */
__HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
}
}
/* check MDIOS WAKEUP exti flag */
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET)
{
/* MDIOS WAKEUP interrupt user callback */
HAL_MDIOS_WakeUpCallback(hmdios);
/* Clear MDIOS WAKEUP Exti pending bit */
__HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG();
}
}
/**
* @brief Write Complete Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
*/
}
/**
* @brief Read Complete Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
*/
}
/**
* @brief Error Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ErrorCallback can be implemented in the user file
*/
}
/**
* @brief MDIOS WAKEUP interrupt callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MDIOS_WakeUpCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
* @brief MDIOS control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the MDIOS.
(+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
(+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.
@endverbatim
* @{
*/
/**
* @brief Gets MDIOS error flags
* @param hmdios: mdios handle
* @retval bit map of occured errors
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
{
/* return errors flags on status register */
return hmdios->Instance->SR;
}
/**
* @brief Return the MDIOS HAL state
* @param hmdios: mdios handle
* @retval MDIOS state
*/
HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
{
/* Return MDIOS state */
return hmdios->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* MDIOS */
#endif /* HAL_MDIOS_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_mmc.c
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_msp_template.c
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/**
******************************************************************************
* @file stm32f7xx_hal_msp_template.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief HAL MSP module.
* This file template is located in the HAL folder and should be copied
* to the user folder.
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup HAL_MSP HAL MSP
* @brief HAL MSP module.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup HAL_MSP_Private_Functions HAL MSP Private Functions
* @{
*/
/**
* @brief Initializes the Global MSP.
* @retval None
*/
void HAL_MspInit(void)
{
}
/**
* @brief DeInitializes the Global MSP.
* @retval None
*/
void HAL_MspDeInit(void)
{
}
/**
* @brief Initializes the PPP MSP.
* @retval None
*/
void HAL_PPP_MspInit(void)
{
}
/**
* @brief DeInitializes the PPP MSP.
* @retval None
*/
void HAL_PPP_MspDeInit(void)
{
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Extended features functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup PCDEx PCDEx
* @brief PCD Extended HAL module driver
* @{
*/
#ifdef HAL_PCD_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @brief PCDEx control functions
*
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Update FIFO configuration
@endverbatim
* @{
*/
/**
* @brief Set Tx FIFO
* @param hpcd: PCD handle
* @param fifo: The number of Tx fifo
* @param size: Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
{
uint8_t i = 0;
uint32_t Tx_Offset = 0;
/* TXn min size = 16 words. (n : Transmit FIFO index)
When a TxFIFO is not used, the Configuration should be as follows:
case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txm can use the space allocated for Txn.
case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
--> Txn should be configured with the minimum space of 16 words
The FIFO is used optimally when used TxFIFOs are allocated in the top
of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
Tx_Offset = hpcd->Instance->GRXFSIZ;
if(fifo == 0)
{
hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
else
{
Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
for (i = 0; i < (fifo - 1); i++)
{
Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
}
/* Multiply Tx_Size by 2 to get higher performance */
hpcd->Instance->DIEPTXF[fifo - 1] = (uint32_t)(((uint32_t)size << 16) | Tx_Offset);
}
return HAL_OK;
}
/**
* @brief Set Rx FIFO
* @param hpcd: PCD handle
* @param size: Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
{
hpcd->Instance->GRXFSIZ = size;
return HAL_OK;
}
/**
* @brief Activate LPM Feature
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = ENABLE;
hpcd->LPM_State = LPM_L0;
USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
/**
* @brief DeActivate LPM feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->lpm_active = DISABLE;
USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
return HAL_OK;
}
#if defined (USB_OTG_GCCFG_BCDEN)
/**
* @brief Handle BatteryCharging Process.
* @param hpcd: PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t tickstart = HAL_GetTick();
/* Start BCD When device is connected */
if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
{
/* Enable DCD : Data Contact Detect */
USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
/* Wait Detect flag or a timeout is happen*/
while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > 1000)
{
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
return;
}
}
/* Right response got */
HAL_Delay(100);
/* Check Detect flag*/
if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
{
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
}
/*Primary detection: checks if connected to Standard Downstream Port
(without charging capability) */
USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
USBx->GCCFG |= USB_OTG_GCCFG_PDEN;
HAL_Delay(100);
if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
{
/* Case of Standard Downstream Port */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
}
else
{
/* start secondary detection to check connection to Charging Downstream
Port or Dedicated Charging Port */
USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
USBx->GCCFG |= USB_OTG_GCCFG_SDEN;
HAL_Delay(100);
if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
{
/* case Dedicated Charging Port */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
}
else
{
/* case Charging Downstream Port */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
}
}
/* Battery Charging capability discovery finished */
HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
}
}
/**
* @brief Activate BatteryCharging feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = ENABLE;
USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
return HAL_OK;
}
/**
* @brief Deactivate BatteryCharging feature.
* @param hpcd: PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
{
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = DISABLE;
USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
return HAL_OK;
}
/**
* @brief Send BatteryCharging message to user layer callback.
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_PCDEx_BCD_Callback could be implemented in the user file
*/
}
#endif /* USB_OTG_GCCFG_BCDEN */
/**
* @brief Send LPM message to user layer callback.
* @param hpcd: PCD handle
* @param msg: LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
UNUSED(msg);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCDEx_LPM_Callback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_pwr.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup PWR PWR
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup PWR_Private_Constants
* @{
*/
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000U)
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
* @{
*/
#define PWR_EWUP_MASK ((uint32_t)0x00003F00)
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
After reset, the backup domain (RTC registers, RTC backup data
registers and backup SRAM) is protected against possible unwanted
write accesses.
To enable access to the RTC Domain and RTC registers, proceed as follows:
(+) Enable the Power Controller (PWR) APB1 interface clock using the
__HAL_RCC_PWR_CLK_ENABLE() macro.
(+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
@endverbatim
* @{
*/
/**
* @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
* @retval None
*/
void HAL_PWR_DeInit(void)
{
__HAL_RCC_PWR_FORCE_RESET();
__HAL_RCC_PWR_RELEASE_RESET();
}
/**
* @brief Enables access to the backup domain (RTC registers, RTC
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_EnableBkUpAccess(void)
{
/* Enable access to RTC and backup registers */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disables access to the backup domain (RTC registers, RTC
* backup data registers and backup SRAM).
* @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the
* Backup Domain Access should be kept enabled.
* @retval None
*/
void HAL_PWR_DisableBkUpAccess(void)
{
/* Disable access to RTC and backup registers */
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @}
*/
/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @brief Low Power modes configuration functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
*** PVD configuration ***
=========================
[..]
(+) The PVD is used to monitor the VDD power supply by comparing it to a
threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled. This is done through
__HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
(+) The PVD is stopped in Standby mode.
*** Wake-up pin configuration ***
================================
[..]
(+) Wake-up pin is used to wake up the system from Standby mode. This pin is
forced in input pull-down configuration and is active on rising edges.
(+) There are up to 6 Wake-up pin in the STM32F7 devices family
*** Low Power modes configuration ***
=====================================
[..]
The devices feature 3 low-power modes:
(+) Sleep mode: Cortex-M7 core stopped, peripherals kept running.
(+) Stop mode: all clocks are stopped, regulator running, regulator
in low power mode
(+) Standby mode: 1.2V domain powered off.
*** Sleep mode ***
==================
[..]
(+) Entry:
The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
functions with
(++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
(++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-@@- The Regulator parameter is not used for the STM32F7 family
and is kept as parameter just to maintain compatibility with the
lower power families (STM32L).
(+) Exit:
Any peripheral interrupt acknowledged by the nested vectored interrupt
controller (NVIC) can wake up the device from Sleep mode.
*** Stop mode ***
=================
[..]
In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
and the HSE RC oscillators are disabled. Internal SRAM and register contents
are preserved.
The voltage regulator can be configured either in normal or low-power mode.
To minimize the consumption In Stop mode, FLASH can be powered off before
entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
It can be switched on again by software after exiting the Stop mode using
the HAL_PWREx_DisableFlashPowerDown() function.
(+) Entry:
The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON)
function with:
(++) Main regulator ON.
(++) Low Power regulator ON.
(+) Exit:
Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
*** Standby mode ***
====================
[..]
(+)
The Standby mode allows to achieve the lowest power consumption. It is based
on the Cortex-M7 deep sleep mode, with the voltage regulator disabled.
The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and
the HSE oscillator are also switched off. SRAM and register contents are lost
except for the RTC registers, RTC backup registers, backup SRAM and Standby
circuitry.
The voltage regulator is OFF.
(++) Entry:
(+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
(++) Exit:
(+++) WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
wakeup, tamper event, time stamp event, external reset in NRST pin, IWDG reset.
*** Auto-wakeup (AWU) from low-power mode ***
=============================================
[..]
(+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
Wakeup event, a tamper event or a time-stamp event, without depending on
an external interrupt (Auto-wakeup mode).
(+) RTC auto-wakeup (AWU) from the Stop and Standby modes
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
is necessary to configure the RTC to detect the tamper or time stamp event using the
HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
@endverbatim
* @{
*/
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
* @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
* information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
* detection level.
* @retval None
*/
void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
{
/* Check the parameters */
assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
/* Set PLS[7:5] bits according to PVDLevel value */
MODIFY_REG(PWR->CR1, PWR_CR1_PLS, sConfigPVD->PVDLevel);
/* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVD_EXTI_DISABLE_EVENT();
__HAL_PWR_PVD_EXTI_DISABLE_IT();
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
/* Configure interrupt mode */
if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
{
__HAL_PWR_PVD_EXTI_ENABLE_IT();
}
/* Configure event mode */
if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
{
__HAL_PWR_PVD_EXTI_ENABLE_EVENT();
}
/* Configure the edge */
if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
}
if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
{
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
}
}
/**
* @brief Enables the Power Voltage Detector(PVD).
* @retval None
*/
void HAL_PWR_EnablePVD(void)
{
/* Enable the power voltage detector */
SET_BIT(PWR->CR1, PWR_CR1_PVDE);
}
/**
* @brief Disables the Power Voltage Detector(PVD).
* @retval None
*/
void HAL_PWR_DisablePVD(void)
{
/* Disable the power voltage detector */
CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);
}
/**
* @brief Enable the WakeUp PINx functionality.
* @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values, which sets the default polarity:
* detection on high level (rising edge):
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
* or one of the following value where the user can explicitly states the enabled pin and
* the chosen polarity
* @arg PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
* @arg PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
* @arg PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
* @arg PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
* @arg PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW
* @arg PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
/* Enable wake-up pin */
SET_BIT(PWR->CSR2, (PWR_EWUP_MASK & WakeUpPinPolarity));
/* Specifies the Wake-Up pin polarity for the event detection
(rising or falling edge) */
MODIFY_REG(PWR->CR2, (PWR_EWUP_MASK & WakeUpPinPolarity), (WakeUpPinPolarity >> 0x06));
}
/**
* @brief Disables the WakeUp PINx functionality.
* @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @arg PWR_WAKEUP_PIN2
* @arg PWR_WAKEUP_PIN3
* @arg PWR_WAKEUP_PIN4
* @arg PWR_WAKEUP_PIN5
* @arg PWR_WAKEUP_PIN6
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
{
assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
CLEAR_BIT(PWR->CSR2, WakeUpPinx);
}
/**
* @brief Enters Sleep mode.
*
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
*
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with
* systick interrupt when used as time base for Timeout
*
* @param Regulator: Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
* @note This parameter is not used for the STM32F7 family and is kept as parameter
* just to maintain compatibility with the lower power families.
* @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
* @retval None
*/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
{
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
/**
* @brief Enters Stop mode.
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock.
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
* @param Regulator: Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
* @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
* @retval None
*/
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
uint32_t tmpreg = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Select the regulator state in Stop mode ---------------------------------*/
tmpreg = PWR->CR1;
/* Clear PDDS and LPDS bits */
tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
/* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
tmpreg |= Regulator;
/* Store the new value */
PWR->CR1 = tmpreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
}
/**
* @brief Enters Standby mode.
* @note In Standby mode, all I/O pins are high impedance except for:
* - Reset pad (still available)
* - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
* Alarm out, or RTC clock calibration out.
* - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.
* - WKUP pins if enabled.
* @retval None
*/
void HAL_PWR_EnterSTANDBYMode(void)
{
/* Select Standby mode */
PWR->CR1 |= PWR_CR1_PDDS;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* This option is used to ensure that store operations are completed */
#if defined ( __CC_ARM)
__force_stores();
#endif
/* Request Wait For Interrupt */
__WFI();
}
/**
* @brief This function handles the PWR PVD interrupt request.
* @note This API should be called under the PVD_IRQHandler().
* @retval None
*/
void HAL_PWR_PVD_IRQHandler(void)
{
/* Check PWR Exti flag */
if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
{
/* PWR PVD interrupt user callback */
HAL_PWR_PVDCallback();
/* Clear PWR Exti pending bit */
__HAL_PWR_PVD_EXTI_CLEAR_FLAG();
}
}
/**
* @brief PWR PVD interrupt callback
* @retval None
*/
__weak void HAL_PWR_PVDCallback(void)
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PWR_PVDCallback could be implemented in the user file
*/
}
/**
* @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode.
* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* Setting this bit is useful when the processor is expected to run only on
* interruptions handling.
* @retval None
*/
void HAL_PWR_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode.
* @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor
* re-enters SLEEP mode when an interruption handling is over.
* @retval None
*/
void HAL_PWR_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enables CORTEX M4 SEVONPEND bit.
* @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_EnableSEVOnPend(void)
{
/* Set SEVONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Disables CORTEX M4 SEVONPEND bit.
* @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes
* WFE to wake up when an interrupt moves from inactive to pended.
* @retval None
*/
void HAL_PWR_DisableSEVOnPend(void)
{
/* Clear SEVONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_pwr_ex.c
Executable
+572
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@@ -0,0 +1,572 @@
/**
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
* + Peripheral Extended features functions
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup PWREx PWREx
* @brief PWR HAL module driver
* @{
*/
#ifdef HAL_PWR_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @addtogroup PWREx_Private_Constants
* @{
*/
#define PWR_OVERDRIVE_TIMEOUT_VALUE 1000
#define PWR_UDERDRIVE_TIMEOUT_VALUE 1000
#define PWR_BKPREG_TIMEOUT_VALUE 1000
#define PWR_VOSRDY_TIMEOUT_VALUE 1000
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
* @{
*/
/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions
* @brief Peripheral Extended features functions
*
@verbatim
===============================================================================
##### Peripheral extended features functions #####
===============================================================================
*** Main and Backup Regulators configuration ***
================================================
[..]
(+) The backup domain includes 4 Kbytes of backup SRAM accessible only from
the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is
retained even in Standby or VBAT mode when the low power backup regulator
is enabled. It can be considered as an internal EEPROM when VBAT is
always present. You can use the HAL_PWREx_EnableBkUpReg() function to
enable the low power backup regulator.
(+) When the backup domain is supplied by VDD (analog switch connected to VDD)
the backup SRAM is powered from VDD which replaces the VBAT power supply to
save battery life.
(+) The backup SRAM is not mass erased by a tamper event. It is read
protected to prevent confidential data, such as cryptographic private
key, from being accessed. The backup SRAM can be erased only through
the Flash interface when a protection level change from level 1 to
level 0 is requested.
-@- Refer to the description of Read protection (RDP) in the Flash
programming manual.
(+) The main internal regulator can be configured to have a tradeoff between
performance and power consumption when the device does not operate at
the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG()
macro which configure VOS bit in PWR_CR register
Refer to the product datasheets for more details.
*** FLASH Power Down configuration ****
=======================================
[..]
(+) By setting the FPDS bit in the PWR_CR register by using the
HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power
down mode when the device enters Stop mode. When the Flash memory
is in power down mode, an additional startup delay is incurred when
waking up from Stop mode.
*** Over-Drive and Under-Drive configuration ****
=================================================
[..]
(+) In Run mode: the main regulator has 2 operating modes available:
(++) Normal mode: The CPU and core logic operate at maximum frequency at a given
voltage scaling (scale 1, scale 2 or scale 3)
(++) Over-drive mode: This mode allows the CPU and the core logic to operate at a
higher frequency than the normal mode for a given voltage scaling (scale 1,
scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow
the sequence described in Reference manual.
(+) In Stop mode: the main regulator or low power regulator supplies a low power
voltage to the 1.2V domain, thus preserving the content of registers
and internal SRAM. 2 operating modes are available:
(++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only
available when the main regulator or the low power regulator is used in Scale 3 or
low voltage mode.
(++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
available when the main regulator or the low power regulator is in low voltage mode.
@endverbatim
* @{
*/
/**
* @brief Enables the Backup Regulator.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
{
uint32_t tickstart = 0;
/* Enable Backup regulator */
PWR->CSR1 |= PWR_CSR1_BRE;
/* Workaround for the following hardware bug: */
/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
PWR->CSR1 |= PWR_CSR1_EIWUP;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till Backup regulator ready flag is set */
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
{
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Disables the Backup Regulator.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
{
uint32_t tickstart = 0;
/* Disable Backup regulator */
PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
/* Workaround for the following hardware bug: */
/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
PWR->CSR1 |= PWR_CSR1_EIWUP;
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till Backup regulator ready flag is set */
while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
{
if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Enables the Flash Power Down in Stop mode.
* @retval None
*/
void HAL_PWREx_EnableFlashPowerDown(void)
{
/* Enable the Flash Power Down */
PWR->CR1 |= PWR_CR1_FPDS;
}
/**
* @brief Disables the Flash Power Down in Stop mode.
* @retval None
*/
void HAL_PWREx_DisableFlashPowerDown(void)
{
/* Disable the Flash Power Down */
PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_FPDS);
}
/**
* @brief Enables Main Regulator low voltage mode.
* @retval None
*/
void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
{
/* Enable Main regulator low voltage */
PWR->CR1 |= PWR_CR1_MRUDS;
}
/**
* @brief Disables Main Regulator low voltage mode.
* @retval None
*/
void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
{
/* Disable Main regulator low voltage */
PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_MRUDS);
}
/**
* @brief Enables Low Power Regulator low voltage mode.
* @retval None
*/
void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
{
/* Enable low power regulator */
PWR->CR1 |= PWR_CR1_LPUDS;
}
/**
* @brief Disables Low Power Regulator low voltage mode.
* @retval None
*/
void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
{
/* Disable low power regulator */
PWR->CR1 &= (uint32_t)~((uint32_t)PWR_CR1_LPUDS);
}
/**
* @brief Activates the Over-Drive mode.
* @note This mode allows the CPU and the core logic to operate at a higher frequency
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
* @note It is recommended to enter or exit Over-drive mode when the application is not running
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
uint32_t tickstart = 0;
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable the Over-drive to extend the clock frequency to 216 MHz */
__HAL_PWR_OVERDRIVE_ENABLE();
/* Get tick */
tickstart = HAL_GetTick();
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
/* Get tick */
tickstart = HAL_GetTick();
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Deactivates the Over-Drive mode.
* @note This mode allows the CPU and the core logic to operate at a higher frequency
* than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).
* @note It is recommended to enter or exit Over-drive mode when the application is not running
* critical tasks and when the system clock source is either HSI or HSE.
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
{
uint32_t tickstart = 0;
__HAL_RCC_PWR_CLK_ENABLE();
/* Disable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Disable the Over-drive */
__HAL_PWR_OVERDRIVE_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_OK;
}
/**
* @brief Enters in Under-Drive STOP mode.
*
* @note This mode can be selected only when the Under-Drive is already active
*
* @note This mode is enabled only with STOP low power mode.
* In this mode, the 1.2V domain is preserved in reduced leakage mode. This
* mode is only available when the main regulator or the low power regulator
* is in low voltage mode
*
* @note If the Under-drive mode was enabled, it is automatically disabled after
* exiting Stop mode.
* When the voltage regulator operates in Under-drive mode, an additional
* startup delay is induced when waking up from Stop mode.
*
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
*
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock.
*
* @note When the voltage regulator operates in low power mode, an additional
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
*
* @param Regulator: specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
* @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
* @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
* @retval None
*/
HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
uint32_t tempreg = 0;
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable the Under-drive Mode ---------------------------------------------*/
/* Clear Under-drive flag */
__HAL_PWR_CLEAR_ODRUDR_FLAG();
/* Enable the Under-drive */
__HAL_PWR_UNDERDRIVE_ENABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait for UnderDrive mode is ready */
while(__HAL_PWR_GET_FLAG(PWR_FLAG_UDRDY))
{
if((HAL_GetTick() - tickstart ) > PWR_UDERDRIVE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Select the regulator state in STOP mode ---------------------------------*/
tempreg = PWR->CR1;
/* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
tempreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS);
/* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
tempreg |= Regulator;
/* Store the new value */
PWR->CR1 = tempreg;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
/* Select STOP mode entry --------------------------------------------------*/
if(STOPEntry == PWR_SLEEPENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
return HAL_OK;
}
/**
* @brief Returns Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or
* PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1
*/
uint32_t HAL_PWREx_GetVoltageRange(void)
{
return (PWR->CR1 & PWR_CR1_VOS);
}
/**
* @brief Configures the main internal regulator output voltage.
* @param VoltageScaling: specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
* typical output voltage at 1.4 V,
* system frequency up to 216 MHz.
* @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
* typical output voltage at 1.2 V,
* system frequency up to 180 MHz.
* @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 2 mode,
* typical output voltage at 1.00 V,
* system frequency up to 151 MHz.
* @note To update the system clock frequency(SYSCLK):
* - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
* - Call the HAL_RCC_OscConfig() to configure the PLL.
* - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
* - Set the new system clock frequency using the HAL_RCC_ClockConfig().
* @note The scale can be modified only when the HSI or HSE clock source is selected
* as system clock source, otherwise the API returns HAL_ERROR.
* @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
* value in the PWR_CR1 register are not taken in account.
* @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
* @note The new voltage scale is active only when the PLL is ON.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
uint32_t tickstart = 0;
assert_param(IS_PWR_REGULATOR_VOLTAGE(VoltageScaling));
/* Enable Power ctrl clock */
__HAL_RCC_PWR_CLK_ENABLE();
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
{
/* Disable the main PLL */
__HAL_RCC_PLL_DISABLE();
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set Range */
__HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
/* Enable the main PLL */
__HAL_RCC_PLL_ENABLE();
/* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Get Start Tick */
tickstart = HAL_GetTick();
while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
{
if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
return HAL_ERROR;
}
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_PWR_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_rng.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
* + Initialization/de-initialization functions
* + Peripheral Control functions
* + Peripheral State functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The RNG HAL driver can be used as follows:
(#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro
in HAL_RNG_MspInit().
(#) Activate the RNG peripheral using HAL_RNG_Init() function.
(#) Wait until the 32 bit Random Number Generator contains a valid
random data using (polling/interrupt) mode.
(#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup RNG
* @{
*/
#ifdef HAL_RNG_MODULE_ENABLED
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup RNG_Private_Constants
* @{
*/
#define RNG_TIMEOUT_VALUE 2
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Private functions prototypes ----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_Exported_Functions
* @{
*/
/** @addtogroup RNG_Exported_Functions_Group1
* @brief Initialization and de-initialization functions
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the RNG according to the specified parameters
in the RNG_InitTypeDef and create the associated handle
(+) DeInitialize the RNG peripheral
(+) Initialize the RNG MSP
(+) DeInitialize RNG MSP
@endverbatim
* @{
*/
/**
* @brief Initializes the RNG peripheral and creates the associated handle.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
{
/* Check the RNG handle allocation */
if(hrng == NULL)
{
return HAL_ERROR;
}
__HAL_LOCK(hrng);
if(hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Enable the RNG Peripheral */
__HAL_RNG_ENABLE(hrng);
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
__HAL_UNLOCK(hrng);
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the RNG peripheral.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
{
/* Check the RNG handle allocation */
if(hrng == NULL)
{
return HAL_ERROR;
}
/* Disable the RNG Peripheral */
CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
/* Clear RNG interrupt status flags */
CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
/* DeInit the low level hardware */
HAL_RNG_MspDeInit(hrng);
/* Update the RNG state */
hrng->State = HAL_RNG_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hrng);
/* Return the function status */
return HAL_OK;
}
/**
* @brief Initializes the RNG MSP.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspInit must be implemented in the user file.
*/
}
/**
* @brief DeInitializes the RNG MSP.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspDeInit must be implemented in the user file.
*/
}
/**
* @}
*/
/** @addtogroup RNG_Exported_Functions_Group2
* @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Get the 32 bit Random number
(+) Get the 32 bit Random number with interrupt enabled
(+) Handle RNG interrupt request
@endverbatim
* @{
*/
/**
* @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit: pointer to generated random number variable if successful.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
uint32_t tickstart = 0;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
if(hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Get tick */
tickstart = HAL_GetTick();
/* Check if data register contains valid random data */
while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
{
hrng->State = HAL_RNG_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
return HAL_TIMEOUT;
}
}
/* Get a 32bit Random number */
hrng->RandomNumber = hrng->Instance->DR;
*random32bit = hrng->RandomNumber;
hrng->State = HAL_RNG_STATE_READY;
}
else
{
status = HAL_ERROR;
}
/* Process Unlocked */
__HAL_UNLOCK(hrng);
return status;
}
/**
* @brief Generates a 32-bit random number in interrupt mode.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
__HAL_LOCK(hrng);
/* Check RNG peripheral state */
if(hrng->State == HAL_RNG_STATE_READY)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Process Unlocked */
__HAL_UNLOCK(hrng);
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
__HAL_RNG_ENABLE_IT(hrng);
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hrng);
status = HAL_ERROR;
}
return status;
}
/**
* @brief Handles RNG interrupt request.
* @note In the case of a clock error, the RNG is no more able to generate
* random numbers because the PLL48CLK clock is not correct. User has
* to check that the clock controller is correctly configured to provide
* the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT().
* The clock error has no impact on the previously generated
* random numbers, and the RNG_DR register contents can be used.
* @note In the case of a seed error, the generation of random numbers is
* interrupted as long as the SECS bit is '1'. If a number is
* available in the RNG_DR register, it must not be used because it may
* not have enough entropy. In this case, it is recommended to clear the
* SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable
* the RNG peripheral to reinitialize and restart the RNG.
* @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
* or CEIS are set.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
{
/* RNG clock error interrupt occurred */
if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_ERROR;
HAL_RNG_ErrorCallback(hrng);
/* Clear the clock error flag */
__HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
}
/* Check RNG data ready interrupt occurred */
if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
{
/* Generate random number once, so disable the IT */
__HAL_RNG_DISABLE_IT(hrng);
/* Get the 32bit Random number (DRDY flag automatically cleared) */
hrng->RandomNumber = hrng->Instance->DR;
if(hrng->State != HAL_RNG_STATE_ERROR)
{
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_READY;
/* Data Ready callback */
HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
}
}
}
/**
* @brief Returns generated random number in polling mode (Obsolete)
* Use HAL_RNG_GenerateRandomNumber() API instead.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval Random value
*/
uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
{
if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
{
return hrng->RandomNumber;
}
else
{
return 0;
}
}
/**
* @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
* Use HAL_RNG_GenerateRandomNumber_IT() API instead.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval 32-bit random number
*/
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
uint32_t random32bit = 0;
/* Process locked */
__HAL_LOCK(hrng);
/* Change RNG peripheral state */
hrng->State = HAL_RNG_STATE_BUSY;
/* Get a 32bit Random number */
random32bit = hrng->Instance->DR;
/* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */
__HAL_RNG_ENABLE_IT(hrng);
/* Return the 32 bit random number */
return random32bit;
}
/**
* @brief Read latest generated random number.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval random value
*/
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
{
return(hrng->RandomNumber);
}
/**
* @brief Data Ready callback in non-blocking mode.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @param random32bit: generated random number.
* @retval None
*/
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
}
/**
* @brief RNG error callbacks.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ErrorCallback must be implemented in the user file.
*/
}
/**
* @}
*/
/** @addtogroup RNG_Exported_Functions_Group3
* @brief Peripheral State functions
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Returns the RNG state.
* @param hrng: pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL state
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
{
return hrng->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_RNG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_sai_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief Empty file; This file is no longer used to set synchronization and
* to get SAI block frequency. Its content is now moved to common files
* (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7
* family. It's just kept for compatibility reasons.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_sdram.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control SDRAM memories. It uses the FMC layer functions to interface
with SDRAM devices.
The following sequence should be followed to configure the FMC to interface
with SDRAM memories:
(#) Declare a SDRAM_HandleTypeDef handle structure, for example:
SDRAM_HandleTypeDef hdsram
(++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
values of the structure member.
(++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
base register instance for NOR or SDRAM device
(#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
FMC_SDRAM_TimingTypeDef Timing;
and fill its fields with the allowed values of the structure member.
(#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
performs the following sequence:
(##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
(##) Control register configuration using the FMC SDRAM interface function
FMC_SDRAM_Init()
(##) Timing register configuration using the FMC SDRAM interface function
FMC_SDRAM_Timing_Init()
(##) Program the SDRAM external device by applying its initialization sequence
according to the device plugged in your hardware. This step is mandatory
for accessing the SDRAM device.
(#) At this stage you can perform read/write accesses from/to the memory connected
to the SDRAM Bank. You can perform either polling or DMA transfer using the
following APIs:
(++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
(++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
(#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
structure.
(#) You can continuously monitor the SDRAM device HAL state by calling the function
HAL_SDRAM_GetState()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup SDRAM SDRAM
* @brief SDRAM driver modules
* @{
*/
#ifdef HAL_SDRAM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
* @{
*/
/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
==============================================================================
##### SDRAM Initialization and de_initialization functions #####
==============================================================================
[..]
This section provides functions allowing to initialize/de-initialize
the SDRAM memory
@endverbatim
* @{
*/
/**
* @brief Performs the SDRAM device initialization sequence.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param Timing: Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
{
/* Check the SDRAM handle parameter */
if(hsdram == NULL)
{
return HAL_ERROR;
}
if(hsdram->State == HAL_SDRAM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsdram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspInit(hsdram);
}
/* Initialize the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
/* Initialize SDRAM control Interface */
FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
/* Initialize SDRAM timing Interface */
FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
/* Update the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_READY;
return HAL_OK;
}
/**
* @brief Perform the SDRAM device initialization sequence.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
{
/* Initialize the low level hardware (MSP) */
HAL_SDRAM_MspDeInit(hsdram);
/* Configure the SDRAM registers with their reset values */
FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
/* Reset the SDRAM controller state */
hsdram->State = HAL_SDRAM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief SDRAM MSP Init.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
__weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsdram);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_SDRAM_MspInit could be implemented in the user file
*/
}
/**
* @brief SDRAM MSP DeInit.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
__weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsdram);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_SDRAM_MspDeInit could be implemented in the user file
*/
}
/**
* @brief This function handles SDRAM refresh error interrupt request.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
{
/* Check SDRAM interrupt Rising edge flag */
if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
{
/* SDRAM refresh error interrupt callback */
HAL_SDRAM_RefreshErrorCallback(hsdram);
/* Clear SDRAM refresh error interrupt pending bit */
__FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
}
}
/**
* @brief SDRAM Refresh error callback.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
__weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsdram);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
*/
}
/**
* @brief DMA transfer complete callback.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
__weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
*/
}
/**
* @brief DMA transfer complete error callback.
* @param hdma: DMA handle
* @retval None
*/
__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* NOTE: This function Should not be modified, when the callback is needed,
the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### SDRAM Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the SDRAM memory
@endverbatim
* @{
*/
/**
* @brief Reads 8-bit data buffer from the SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
{
__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
{
return HAL_ERROR;
}
/* Read data from source */
for(; BufferSize != 0; BufferSize--)
{
*pDstBuffer = *(__IO uint8_t *)pSdramAddress;
pDstBuffer++;
pSdramAddress++;
}
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief Writes 8-bit data buffer to SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
{
__IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
uint32_t tmp = 0;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
tmp = hsdram->State;
if(tmp == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
return HAL_ERROR;
}
/* Write data to memory */
for(; BufferSize != 0; BufferSize--)
{
*(__IO uint8_t *)pSdramAddress = *pSrcBuffer;
pSrcBuffer++;
pSdramAddress++;
}
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief Reads 16-bit data buffer from the SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
{
__IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
{
return HAL_ERROR;
}
/* Read data from source */
for(; BufferSize != 0; BufferSize--)
{
*pDstBuffer = *(__IO uint16_t *)pSdramAddress;
pDstBuffer++;
pSdramAddress++;
}
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief Writes 16-bit data buffer to SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
{
__IO uint16_t *pSdramAddress = (uint16_t *)pAddress;
uint32_t tmp = 0;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
tmp = hsdram->State;
if(tmp == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
return HAL_ERROR;
}
/* Write data to memory */
for(; BufferSize != 0; BufferSize--)
{
*(__IO uint16_t *)pSdramAddress = *pSrcBuffer;
pSrcBuffer++;
pSdramAddress++;
}
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief Reads 32-bit data buffer from the SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
{
__IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED)
{
return HAL_ERROR;
}
/* Read data from source */
for(; BufferSize != 0; BufferSize--)
{
*pDstBuffer = *(__IO uint32_t *)pSdramAddress;
pDstBuffer++;
pSdramAddress++;
}
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief Writes 32-bit data buffer to SDRAM memory.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
{
__IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
uint32_t tmp = 0;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
tmp = hsdram->State;
if(tmp == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
return HAL_ERROR;
}
/* Write data to memory */
for(; BufferSize != 0; BufferSize--)
{
*(__IO uint32_t *)pSdramAddress = *pSrcBuffer;
pSrcBuffer++;
pSdramAddress++;
}
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief Reads a Words data from the SDRAM memory using DMA transfer.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
{
uint32_t tmp = 0;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
tmp = hsdram->State;
if(tmp == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if(tmp == HAL_SDRAM_STATE_PRECHARGED)
{
return HAL_ERROR;
}
/* Configure DMA user callbacks */
hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
{
uint32_t tmp = 0;
/* Process Locked */
__HAL_LOCK(hsdram);
/* Check the SDRAM controller state */
tmp = hsdram->State;
if(tmp == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED))
{
return HAL_ERROR;
}
/* Configure DMA user callbacks */
hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
/* Process Unlocked */
__HAL_UNLOCK(hsdram);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup SDRAM_Exported_Functions_Group3 Control functions
* @brief management functions
*
@verbatim
==============================================================================
##### SDRAM Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the SDRAM interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically SDRAM write protection.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
{
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
/* Enable write protection */
FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
return HAL_OK;
}
/**
* @brief Disables dynamically SDRAM write protection.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
{
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
/* Disable write protection */
FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_READY;
return HAL_OK;
}
/**
* @brief Sends Command to the SDRAM bank.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param Command: SDRAM command structure
* @param Timeout: Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
/* Send SDRAM command */
FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
/* Update the SDRAM controller state state */
if(Command->CommandMode == FMC_SDRAM_CMD_PALL)
{
hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
}
else
{
hsdram->State = HAL_SDRAM_STATE_READY;
}
return HAL_OK;
}
/**
* @brief Programs the SDRAM Memory Refresh rate.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param RefreshRate: The SDRAM refresh rate value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
{
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
/* Program the refresh rate */
FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate);
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_READY;
return HAL_OK;
}
/**
* @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @param AutoRefreshNumber: The SDRAM auto Refresh number
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
{
/* Check the SDRAM controller state */
if(hsdram->State == HAL_SDRAM_STATE_BUSY)
{
return HAL_BUSY;
}
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_BUSY;
/* Set the Auto-Refresh number */
FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber);
/* Update the SDRAM state */
hsdram->State = HAL_SDRAM_STATE_READY;
return HAL_OK;
}
/**
* @brief Returns the SDRAM memory current mode.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval The SDRAM memory mode.
*/
uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
{
/* Return the SDRAM memory current mode */
return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
}
/**
* @}
*/
/** @defgroup SDRAM_Exported_Functions_Group4 State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### SDRAM State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the SDRAM controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Returns the SDRAM state.
* @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL state
*/
HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
{
return hsdram->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SDRAM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_smartcard_ex.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief SMARTCARD HAL module driver.
*
* This file provides extended firmware functions to manage the following
* functionalities of the SmartCard.
* + Initialization and de-initialization functions
* + Peripheral Control functions
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The Extended SMARTCARD HAL driver can be used as follow:
(#) After having configured the SMARTCARD basic features with HAL_SMARTCARD_Init(),
then if required, program SMARTCARD advanced features (TX/RX pins swap, TimeOut,
auto-retry counter,...) in the hsc AdvancedInit structure.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup SMARTCARDEx SMARTCARDEx
* @brief SMARTCARD Extended HAL module driver
* @{
*/
#ifdef HAL_SMARTCARD_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions
* @{
*/
/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions
* @brief Extended control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the SMARTCARD.
(+) HAL_SMARTCARDEx_BlockLength_Config() API allows to configure the Block Length on the fly
(+) HAL_SMARTCARDEx_TimeOut_Config() API allows to configure the receiver timeout value on the fly
(+) HAL_SMARTCARDEx_EnableReceiverTimeOut() API enables the receiver timeout feature
(+) HAL_SMARTCARDEx_DisableReceiverTimeOut() API disables the receiver timeout feature
@endverbatim
* @{
*/
/**
* @brief Update on the fly the SMARTCARD block length in RTOR register
* @param hsc: SMARTCARD handle
* @param BlockLength: SMARTCARD block length (8-bit long at most)
* @retval None
*/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength)
{
MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_BLEN, ((uint32_t)BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS));
}
/**
* @brief Update on the fly the receiver timeout value in RTOR register
* @param hsc: SMARTCARD handle
* @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout
* value must be less or equal to 0x0FFFFFFFF.
* @retval None
*/
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsc, uint32_t TimeOutValue)
{
assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue));
MODIFY_REG(hsc->Instance->RTOR, USART_RTOR_RTO, TimeOutValue);
}
/**
* @brief Enable the SMARTCARD receiver timeout feature
* @param hsc: SMARTCARD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)
{
/* Process Locked */
__HAL_LOCK(hsc);
hsc->gState = HAL_SMARTCARD_STATE_BUSY;
/* Set the USART RTOEN bit */
hsc->Instance->CR2 |= USART_CR2_RTOEN;
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
return HAL_OK;
}
/**
* @brief Disable the SMARTCARD receiver timeout feature
* @param hsc: SMARTCARD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)
{
/* Process Locked */
__HAL_LOCK(hsc);
hsc->gState = HAL_SMARTCARD_STATE_BUSY;
/* Clear the USART RTOEN bit */
hsc->Instance->CR2 &= ~(USART_CR2_RTOEN);
hsc->gState = HAL_SMARTCARD_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsc);
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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/**
******************************************************************************
* @file stm32f7xx_hal_sram.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This driver is a generic layered driver which contains a set of APIs used to
control SRAM memories. It uses the FMC layer functions to interface
with SRAM devices.
The following sequence should be followed to configure the FMC to interface
with SRAM/PSRAM memories:
(#) Declare a SRAM_HandleTypeDef handle structure, for example:
SRAM_HandleTypeDef hsram; and:
(++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
values of the structure member.
(++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
base register instance for NOR or SRAM device
(++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
base register instance for NOR or SRAM extended mode
(#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
mode timings; for example:
FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
and fill its fields with the allowed values of the structure member.
(#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
performs the following sequence:
(##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
(##) Control register configuration using the FMC NORSRAM interface function
FMC_NORSRAM_Init()
(##) Timing register configuration using the FMC NORSRAM interface function
FMC_NORSRAM_Timing_Init()
(##) Extended mode Timing register configuration using the FMC NORSRAM interface function
FMC_NORSRAM_Extended_Timing_Init()
(##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
(#) At this stage you can perform read/write accesses from/to the memory connected
to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
following APIs:
(++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
(++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
(#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
(#) You can continuously monitor the SRAM device HAL state by calling the function
HAL_SRAM_GetState()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup SRAM SRAM
* @brief SRAM driver modules
* @{
*/
#ifdef HAL_SRAM_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### SRAM Initialization and de_initialization functions #####
==============================================================================
[..] This section provides functions allowing to initialize/de-initialize
the SRAM memory
@endverbatim
* @{
*/
/**
* @brief Performs the SRAM device initialization sequence
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param Timing: Pointer to SRAM control timing structure
* @param ExtTiming: Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
{
/* Check the SRAM handle parameter */
if(hsram == NULL)
{
return HAL_ERROR;
}
if(hsram->State == HAL_SRAM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsram->Lock = HAL_UNLOCKED;
/* Initialize the low level hardware (MSP) */
HAL_SRAM_MspInit(hsram);
}
/* Initialize SRAM control Interface */
FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
/* Initialize SRAM timing Interface */
FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
/* Initialize SRAM extended mode timing Interface */
FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
return HAL_OK;
}
/**
* @brief Performs the SRAM device De-initialization sequence.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
{
/* De-Initialize the low level hardware (MSP) */
HAL_SRAM_MspDeInit(hsram);
/* Configure the SRAM registers with their reset values */
FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
hsram->State = HAL_SRAM_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief SRAM MSP Init.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsram);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_MspInit could be implemented in the user file
*/
}
/**
* @brief SRAM MSP DeInit.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hsram);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_MspDeInit could be implemented in the user file
*/
}
/**
* @brief DMA transfer complete callback.
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
*/
}
/**
* @brief DMA transfer complete error callback.
* @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hdma);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @brief Input Output and memory control functions
*
@verbatim
==============================================================================
##### SRAM Input and Output functions #####
==============================================================================
[..]
This section provides functions allowing to use and control the SRAM memory
@endverbatim
* @{
*/
/**
* @brief Reads 8-bit buffer from SRAM memory.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
{
__IO uint8_t * psramaddress = (uint8_t *)pAddress;
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
for(; BufferSize != 0; BufferSize--)
{
*pDstBuffer = *(__IO uint8_t *)psramaddress;
pDstBuffer++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Writes 8-bit buffer to SRAM memory.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
{
__IO uint8_t * psramaddress = (uint8_t *)pAddress;
/* Check the SRAM controller state */
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
for(; BufferSize != 0; BufferSize--)
{
*(__IO uint8_t *)psramaddress = *pSrcBuffer;
pSrcBuffer++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Reads 16-bit buffer from SRAM memory.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
{
__IO uint16_t * psramaddress = (uint16_t *)pAddress;
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
for(; BufferSize != 0; BufferSize--)
{
*pDstBuffer = *(__IO uint16_t *)psramaddress;
pDstBuffer++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Writes 16-bit buffer to SRAM memory.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
{
__IO uint16_t * psramaddress = (uint16_t *)pAddress;
/* Check the SRAM controller state */
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
for(; BufferSize != 0; BufferSize--)
{
*(__IO uint16_t *)psramaddress = *pSrcBuffer;
pSrcBuffer++;
psramaddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Reads 32-bit buffer from SRAM memory.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Read data from memory */
for(; BufferSize != 0; BufferSize--)
{
*pDstBuffer = *(__IO uint32_t *)pAddress;
pDstBuffer++;
pAddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Writes 32-bit buffer to SRAM memory.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
{
/* Check the SRAM controller state */
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Write data to memory */
for(; BufferSize != 0; BufferSize--)
{
*(__IO uint32_t *)pAddress = *pSrcBuffer;
pSrcBuffer++;
pAddress++;
}
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Reads a Words data from the SRAM memory using DMA transfer.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to read start address
* @param pDstBuffer: Pointer to destination buffer
* @param BufferSize: Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Configure DMA user callbacks */
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @param pAddress: Pointer to write start address
* @param pSrcBuffer: Pointer to source buffer to write
* @param BufferSize: Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
{
/* Check the SRAM controller state */
if(hsram->State == HAL_SRAM_STATE_PROTECTED)
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Configure DMA user callbacks */
hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
/* Enable the DMA Stream */
HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group3 Control functions
* @brief Control functions
*
@verbatim
==============================================================================
##### SRAM Control functions #####
==============================================================================
[..]
This subsection provides a set of functions allowing to control dynamically
the SRAM interface.
@endverbatim
* @{
*/
/**
* @brief Enables dynamically SRAM write operation.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Enable write operation */
FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @brief Disables dynamically SRAM write operation.
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
{
/* Process Locked */
__HAL_LOCK(hsram);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_BUSY;
/* Disable write operation */
FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
/* Update the SRAM controller state */
hsram->State = HAL_SRAM_STATE_PROTECTED;
/* Process unlocked */
__HAL_UNLOCK(hsram);
return HAL_OK;
}
/**
* @}
*/
/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions
*
@verbatim
==============================================================================
##### SRAM State functions #####
==============================================================================
[..]
This subsection permits to get in run-time the status of the SRAM controller
and the data flow.
@endverbatim
* @{
*/
/**
* @brief Returns the SRAM controller state
* @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL state
*/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
{
return hsram->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_SRAM_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim.c
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_tim_ex.c
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_alarm_template.c
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/**
******************************************************************************
* @file stm32f7xx_hal_timebase_rtc_alarm_template.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief HAL time base based on the hardware RTC_ALARM Template.
*
* This file override the native HAL time base functions (defined as weak)
* to use the RTC ALARM for time base generation:
* + Intializes the RTC peripheral to increment the seconds registers each 1ms
* + The alarm is configured to assert an interrupt when the RTC reaches 1ms
* + HAL_IncTick is called at each Alarm event and the time is reset to 00:00:00
* + HSE (default), LSE or LSI can be selected as RTC clock source
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This file must be copied to the application folder and modified as follows:
(#) Rename it to 'stm32f7xx_hal_timebase_rtc_alarm.c'
(#) Add this file and the RTC HAL drivers to your project and uncomment
HAL_RTC_MODULE_ENABLED define in stm32f7xx_hal_conf.h
[..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources.
Application/Example behavior is no more guaranteed
(@) The stm32f7xx_hal_timebase_tim use is recommended for the Applications/Examples
requiring low power modes
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup HAL_TimeBase_RTC_Alarm_Template HAL TimeBase RTC Alarm Template
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
precision.
+ RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
precision.
*/
#define RTC_CLOCK_SOURCE_HSE
/* #define RTC_CLOCK_SOURCE_LSE */
/* #define RTC_CLOCK_SOURCE_LSI */
#ifdef RTC_CLOCK_SOURCE_HSE
#define RTC_ASYNCH_PREDIV 99U
#define RTC_SYNCH_PREDIV 9U
#define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
#define RTC_ASYNCH_PREDIV 0U
#define RTC_SYNCH_PREDIV 31U
#endif /* RTC_CLOCK_SOURCE_HSE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
RTC_HandleTypeDef hRTC_Handle;
/* Private function prototypes -----------------------------------------------*/
void RTC_Alarm_IRQHandler(void);
/* Private functions ---------------------------------------------------------*/
/**
* @brief This function configures the RTC_ALARMA as a time base source.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
{
__IO uint32_t counter = 0U;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
#ifdef RTC_CLOCK_SOURCE_LSE
/* Configue LSE as RTC clock soucre */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#elif defined (RTC_CLOCK_SOURCE_LSI)
/* Configue LSI as RTC clock soucre */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#elif defined (RTC_CLOCK_SOURCE_HSE)
/* Configue HSE as RTC clock soucre */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
/* Ensure that RTC is clocked by 1MHz */
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ;
#else
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
HSE as RTC clock
Time base = ((99 + 1) * (9 + 1)) / 1MHz
= 1ms
LSE as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32.768KHz
= ~1ms
LSI as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32KHz
= 1ms
*/
hRTC_Handle.Instance = RTC;
hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
HAL_RTC_Init(&hRTC_Handle);
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable the Alarm A interrupt */
__HAL_RTC_ALARMA_DISABLE(&hRTC_Handle);
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_ALRAF);
counter = 0U;
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
while(__HAL_RTC_ALARM_GET_FLAG(&hRTC_Handle, RTC_FLAG_ALRAWF) == RESET)
{
if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
{
return HAL_ERROR;
}
}
hRTC_Handle.Instance->ALRMAR = (uint32_t)0x01U;
/* Configure the Alarm state: Enable Alarm */
__HAL_RTC_ALARMA_ENABLE(&hRTC_Handle);
/* Configure the Alarm interrupt */
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
/* RTC Alarm Interrupt Configuration: EXTI configuration */
__HAL_RTC_ALARM_EXTI_ENABLE_IT();
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();
/* Check if the Initialization mode is set */
if((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
/* Set the Initialization mode */
hRTC_Handle.Instance->ISR = (uint32_t)RTC_INIT_MASK;
counter = 0U;
while((hRTC_Handle.Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
{
return HAL_ERROR;
}
}
}
hRTC_Handle.Instance->DR = 0U;
hRTC_Handle.Instance->TR = 0U;
hRTC_Handle.Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
HAL_NVIC_SetPriority(RTC_Alarm_IRQn, TickPriority, 0U);
HAL_NVIC_EnableIRQ(RTC_Alarm_IRQn);
return HAL_OK;
}
}
return HAL_ERROR;
}
/**
* @brief Suspend Tick increment.
* @note Disable the tick increment by disabling RTC ALARM interrupt.
* @retval None
*/
void HAL_SuspendTick(void)
{
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable RTC ALARM update Interrupt */
__HAL_RTC_ALARM_DISABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
}
/**
* @brief Resume Tick increment.
* @note Enable the tick increment by Enabling RTC ALARM interrupt.
* @retval None
*/
void HAL_ResumeTick(void)
{
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Enable RTC ALARM Update interrupt */
__HAL_RTC_ALARM_ENABLE_IT(&hRTC_Handle, RTC_IT_ALRA);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
}
/**
* @brief ALARM A Event Callback in non blocking mode
* @note This function is called when RTC_ALARM interrupt took place, inside
* RTC_ALARM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param hrtc : RTC handle
* @retval None
*/
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
{
__IO uint32_t counter = 0U;
HAL_IncTick();
__HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
/* Set the Initialization mode */
hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
{
if(counter++ == (SystemCoreClock /48U)) /* Timeout = ~ 1s */
{
break;
}
}
hrtc->Instance->DR = 0U;
hrtc->Instance->TR = 0U;
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
}
/**
* @brief This function handles RTC ALARM interrupt request.
* @retval None
*/
void RTC_Alarm_IRQHandler(void)
{
HAL_RTC_AlarmIRQHandler(&hRTC_Handle);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_rtc_wakeup_template.c
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/**
******************************************************************************
* @file stm32f7xx_hal_timebase_rtc_wakeup_template.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief HAL time base based on the hardware RTC_WAKEUP Template.
*
* This file overrides the native HAL time base functions (defined as weak)
* to use the RTC WAKEUP for the time base generation:
* + Intializes the RTC peripheral and configures the wakeup timer to be
* incremented each 1ms
* + The wakeup feature is configured to assert an interrupt each 1ms
* + HAL_IncTick is called inside the HAL_RTCEx_WakeUpTimerEventCallback
* + HSE (default), LSE or LSI can be selected as RTC clock source
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
This file must be copied to the application folder and modified as follows:
(#) Rename it to 'stm32f7xx_hal_timebase_rtc_wakeup.c'
(#) Add this file and the RTC HAL drivers to your project and uncomment
HAL_RTC_MODULE_ENABLED define in stm32f7xx_hal_conf.h
[..]
(@) HAL RTC alarm and HAL RTC wakeup drivers can’t be used with low power modes:
The wake up capability of the RTC may be intrusive in case of prior low power mode
configuration requiring different wake up sources.
Application/Example behavior is no more guaranteed
(@) The stm32f7xx_hal_timebase_tim use is recommended for the Applications/Examples
requiring low power modes
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup HAL_TimeBase_RTC_WakeUp_Template HAL TimeBase RTC WakeUp Template
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Uncomment the line below to select the appropriate RTC Clock source for your application:
+ RTC_CLOCK_SOURCE_HSE: can be selected for applications requiring timing precision.
+ RTC_CLOCK_SOURCE_LSE: can be selected for applications with low constraint on timing
precision.
+ RTC_CLOCK_SOURCE_LSI: can be selected for applications with low constraint on timing
precision.
*/
#define RTC_CLOCK_SOURCE_HSE
/* #define RTC_CLOCK_SOURCE_LSE */
/* #define RTC_CLOCK_SOURCE_LSI */
#ifdef RTC_CLOCK_SOURCE_HSE
#define RTC_ASYNCH_PREDIV 99U
#define RTC_SYNCH_PREDIV 9U
#define RCC_RTCCLKSOURCE_1MHZ ((uint32_t)((uint32_t)RCC_BDCR_RTCSEL | (uint32_t)((HSE_VALUE/1000000U) << 16U)))
#else /* RTC_CLOCK_SOURCE_LSE || RTC_CLOCK_SOURCE_LSI */
#define RTC_ASYNCH_PREDIV 0U
#define RTC_SYNCH_PREDIV 31U
#endif /* RTC_CLOCK_SOURCE_HSE */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
RTC_HandleTypeDef hRTC_Handle;
/* Private function prototypes -----------------------------------------------*/
void RTC_WKUP_IRQHandler(void);
/* Private functions ---------------------------------------------------------*/
/**
* @brief This function configures the RTC_WKUP as a time base source.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* Wakeup Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
= 1ms
* Wakeup Time = WakeupTimebase * WakeUpCounter (0 + 1)
= 1 ms
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
{
__IO uint32_t counter = 0U;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
#ifdef RTC_CLOCK_SOURCE_LSE
/* Configue LSE as RTC clock soucre */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSEState = RCC_LSE_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
#elif defined (RTC_CLOCK_SOURCE_LSI)
/* Configue LSI as RTC clock soucre */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.LSIState = RCC_LSI_ON;
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI;
#elif defined (RTC_CLOCK_SOURCE_HSE)
/* Configue HSE as RTC clock soucre */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
/* Ensure that RTC is clocked by 1MHz */
PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_1MHZ;
#else
#error Please select the RTC Clock source
#endif /* RTC_CLOCK_SOURCE_LSE */
if(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK)
{
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC;
if(HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) == HAL_OK)
{
/* Enable RTC Clock */
__HAL_RCC_RTC_ENABLE();
/* The time base should be 1ms
Time base = ((RTC_ASYNCH_PREDIV + 1) * (RTC_SYNCH_PREDIV + 1)) / RTC_CLOCK
HSE as RTC clock
Time base = ((99 + 1) * (9 + 1)) / 1Mhz
= 1ms
LSE as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32.768Khz
= ~1ms
LSI as RTC clock
Time base = ((31 + 1) * (0 + 1)) / 32Khz
= 1ms
*/
hRTC_Handle.Instance = RTC;
hRTC_Handle.Init.HourFormat = RTC_HOURFORMAT_24;
hRTC_Handle.Init.AsynchPrediv = RTC_ASYNCH_PREDIV;
hRTC_Handle.Init.SynchPrediv = RTC_SYNCH_PREDIV;
hRTC_Handle.Init.OutPut = RTC_OUTPUT_DISABLE;
hRTC_Handle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
hRTC_Handle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
HAL_RTC_Init(&hRTC_Handle);
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_DISABLE(&hRTC_Handle);
/* In case of interrupt mode is used, the interrupt source must disabled */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle,RTC_IT_WUT);
/* Wait till RTC WUTWF flag is set */
while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(&hRTC_Handle, RTC_FLAG_WUTWF) == RESET)
{
if(counter++ == (SystemCoreClock /48U))
{
return HAL_ERROR;
}
}
/* Clear PWR wake up Flag */
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WU);
/* Clear RTC Wake Up timer Flag */
__HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(&hRTC_Handle, RTC_FLAG_WUTF);
/* Configure the Wake-up Timer counter */
hRTC_Handle.Instance->WUTR = (uint32_t)0U;
/* Clear the Wake-up Timer clock source bits in CR register */
hRTC_Handle.Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
/* Configure the clock source */
hRTC_Handle.Instance->CR |= (uint32_t)RTC_WAKEUPCLOCK_CK_SPRE_16BITS;
/* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT();
__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Configure the Interrupt in the RTC_CR register */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle,RTC_IT_WUT);
/* Enable the Wake-up Timer */
__HAL_RTC_WAKEUPTIMER_ENABLE(&hRTC_Handle);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
HAL_NVIC_SetPriority(RTC_WKUP_IRQn, TickPriority, 0U);
HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn);
return HAL_OK;
}
}
return HAL_ERROR;
}
/**
* @brief Suspend Tick increment.
* @note Disable the tick increment by disabling RTC_WKUP interrupt.
* @retval None
*/
void HAL_SuspendTick(void)
{
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Disable WAKE UP TIMER Interrupt */
__HAL_RTC_WAKEUPTIMER_DISABLE_IT(&hRTC_Handle, RTC_IT_WUT);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
}
/**
* @brief Resume Tick increment.
* @note Enable the tick increment by Enabling RTC_WKUP interrupt.
* @retval None
*/
void HAL_ResumeTick(void)
{
/* Disable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_DISABLE(&hRTC_Handle);
/* Enable WAKE UP TIMER interrupt */
__HAL_RTC_WAKEUPTIMER_ENABLE_IT(&hRTC_Handle, RTC_IT_WUT);
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(&hRTC_Handle);
}
/**
* @brief Wake Up Timer Event Callback in non blocking mode
* @note This function is called when RTC_WKUP interrupt took place, inside
* RTC_WKUP_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param hrtc : RTC handle
* @retval None
*/
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
{
HAL_IncTick();
}
/**
* @brief This function handles WAKE UP TIMER interrupt request.
* @retval None
*/
void RTC_WKUP_IRQHandler(void)
{
HAL_RTCEx_WakeUpTimerIRQHandler(&hRTC_Handle);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_timebase_tim_template.c
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/**
******************************************************************************
* @file stm32f7xx_hal_timebase_tim_template.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief HAL time base based on the hardware TIM Template.
*
* This file overrides the native HAL time base functions (defined as weak)
* the TIM time base:
* + Intializes the TIM peripheral generate a Period elapsed Event each 1ms
* + HAL_IncTick is called inside HAL_TIM_PeriodElapsedCallback ie each 1ms
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup HAL_TimeBase
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
TIM_HandleTypeDef TimHandle;
/* Private function prototypes -----------------------------------------------*/
void TIM6_DAC_IRQHandler(void);
/* Private functions ---------------------------------------------------------*/
/**
* @brief This function configures the TIM6 as a time base source.
* The time source is configured to have 1ms time base with a dedicated
* Tick interrupt priority.
* @note This function is called automatically at the beginning of program after
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority)
{
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
uint32_t uwPrescalerValue = 0U;
uint32_t pFLatency;
/*Configure the TIM6 IRQ priority */
HAL_NVIC_SetPriority(TIM6_DAC_IRQn, TickPriority ,0U);
/* Enable the TIM6 global Interrupt */
HAL_NVIC_EnableIRQ(TIM6_DAC_IRQn);
/* Enable TIM6 clock */
__HAL_RCC_TIM6_CLK_ENABLE();
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
/* Compute TIM6 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
}
else
{
uwTimclock = 2*HAL_RCC_GetPCLK1Freq();
}
/* Compute the prescaler value to have TIM6 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
/* Initialize TIM6 */
TimHandle.Instance = TIM6;
/* Initialize TIMx peripheral as follow:
+ Period = [(TIM6CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
TimHandle.Init.Period = (1000000U / 1000U) - 1U;
TimHandle.Init.Prescaler = uwPrescalerValue;
TimHandle.Init.ClockDivision = 0;
TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
if(HAL_TIM_Base_Init(&TimHandle) == HAL_OK)
{
/* Start the TIM time Base generation in interrupt mode */
return HAL_TIM_Base_Start_IT(&TimHandle);
}
/* Return function status */
return HAL_ERROR;
}
/**
* @brief Suspend Tick increment.
* @note Disable the tick increment by disabling TIM6 update interrupt.
* @retval None
*/
void HAL_SuspendTick(void)
{
/* Disable TIM6 update Interrupt */
__HAL_TIM_DISABLE_IT(&TimHandle, TIM_IT_UPDATE);
}
/**
* @brief Resume Tick increment.
* @note Enable the tick increment by Enabling TIM6 update interrupt.
* @retval None
*/
void HAL_ResumeTick(void)
{
/* Enable TIM6 Update interrupt */
__HAL_TIM_ENABLE_IT(&TimHandle, TIM_IT_UPDATE);
}
/**
* @brief Period elapsed callback in non blocking mode
* @note This function is called when TIM6 interrupt took place, inside
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
HAL_IncTick();
}
/**
* @brief This function handles TIM interrupt request.
* @retval None
*/
void TIM6_DAC_IRQHandler(void)
{
HAL_TIM_IRQHandler(&TimHandle);
}
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_uart.c
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_usart.c
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_wwdg.c
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/**
******************************************************************************
* @file stm32f7xx_hal_wwdg.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief WWDG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Window Watchdog (WWDG) peripheral:
* + Initialization and Configuration function
* + IO operation functions
@verbatim
==============================================================================
##### WWDG specific features #####
==============================================================================
[..]
Once enabled the WWDG generates a system reset on expiry of a programmed
time period, unless the program refreshes the counter (T[6;0] downcounter)
before reaching 0x3F value (i.e. a reset is generated when the counter
value rolls over from 0x40 to 0x3F).
(+) An MCU reset is also generated if the counter value is refreshed
before the counter has reached the refresh window value. This
implies that the counter must be refreshed in a limited window.
(+) Once enabled the WWDG cannot be disabled except by a system reset.
(+) WWDGRST flag in RCC_CSR register informs when a WWDG reset has
occurred (check available with __HAL_RCC_GET_FLAG(RCC_FLAG_WWDGRST)).
(+) The WWDG downcounter input clock is derived from the APB clock divided
by a programmable prescaler.
(+) WWDG downcounter clock (Hz) = PCLK1 / (4096 * Prescaler)
(+) WWDG timeout (ms) = (1000 * (T[5;0] + 1)) / (WWDG downcounter clock)
where T[5;0] are the lowest 6 bits of downcounter.
(+) WWDG Counter refresh is allowed between the following limits :
(++) min time (ms) = (1000 * (T[5;0] - Window)) / (WWDG downcounter clock)
(++) max time (ms) = (1000 * (T[5;0] - 0x40)) / (WWDG downcounter clock)
(+) Min-max timeout value @80 MHz(PCLK1): ~51.2 us / ~26.22 ms
(+) The Early Wakeup Interrupt (EWI) can be used if specific safety
operations or data logging must be performed before the actual reset is
generated. When the downcounter reaches the value 0x40, an EWI interrupt
is generated and the corresponding interrupt service routine (ISR) can
be used to trigger specific actions (such as communications or data
logging), before resetting the device.
In some applications, the EWI interrupt can be used to manage a software
system check and/or system recovery/graceful degradation, without
generating a WWDG reset. In this case, the corresponding interrupt
service routine (ISR) should reload the WWDG counter to avoid the WWDG
reset, then trigger the required actions.
Note:When the EWI interrupt cannot be served, e.g. due to a system lock
in a higher priority task, the WWDG reset will eventually be generated.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the WWDG counter either continues to work normally or stops, depending
on DBG_WWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_WWDG() and __HAL_DBGMCU_UNFREEZE_WWDG() macros
##### How to use this driver #####
==============================================================================
[..]
(+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE().
(+) Set the WWDG prescaler, refresh window, counter value and Early Wakeup
Interrupt mode using using HAL_WWDG_Init() function.
This enables WWDG peripheral and the downcounter starts downcounting
from given counter value.
Init function can be called again to modify all watchdog parameters,
however if EWI mode has been set once, it can't be clear until next
reset.
(+) The application program must refresh the WWDG counter at regular
intervals during normal operation to prevent an MCU reset using
HAL_WWDG_Refresh() function. This operation must occur only when
the counter is lower than the window value already programmed.
(+) if Early Wakeup Interrupt mode is enable an interrupt is generated when
the counter reaches 0x40. User can add his own code in weak function
HAL_WWDG_EarlyWakeupCallback().
*** WWDG HAL driver macros list ***
==================================
[..]
Below the list of most used macros in WWDG HAL driver.
(+) __HAL_WWDG_GET_IT_SOURCE: Check the selected WWDG's interrupt source.
(+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status.
(+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#ifdef HAL_WWDG_MODULE_ENABLED
/** @defgroup WWDG WWDG
* @brief WWDG HAL module driver.
* @{
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions.
*
@verbatim
==============================================================================
##### Initialization and Configuration functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Initialize and start the WWDG according to the specified parameters
in the WWDG_InitTypeDef of associated handle.
(+) Initialize the WWDG MSP.
@endverbatim
* @{
*/
/**
* @brief Initialize the WWDG according to the specified.
* parameters in the WWDG_InitTypeDef of associated handle.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
{
/* Check the WWDG handle allocation */
if(hwwdg == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window));
assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter));
assert_param(IS_WWDG_EWI_MODE(hwwdg->Init.EWIMode));
/* Init the low level hardware */
HAL_WWDG_MspInit(hwwdg);
/* Set WWDG Counter */
WRITE_REG(hwwdg->Instance->CR, (WWDG_CR_WDGA | hwwdg->Init.Counter));
/* Set WWDG Prescaler and Window */
WRITE_REG(hwwdg->Instance->CFR, (hwwdg->Init.EWIMode | hwwdg->Init.Prescaler | hwwdg->Init.Window));
/* Return function status */
return HAL_OK;
}
/**
* @brief Initialize the WWDG MSP.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @note When rewriting this function in user file, mechanism may be added
* to avoid multiple initialize when HAL_WWDG_Init function is called
* again to change parameters.
* @retval None
*/
__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_MspInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
*
@verbatim
==============================================================================
##### IO operation functions #####
==============================================================================
[..]
This section provides functions allowing to:
(+) Refresh the WWDG.
(+) Handle WWDG interrupt request and associated function callback.
@endverbatim
* @{
*/
/**
* @brief Refresh the WWDG.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg)
{
/* Write to WWDG CR the WWDG Counter value to refresh with */
WRITE_REG(hwwdg->Instance->CR, (hwwdg->Init.Counter));
/* Return function status */
return HAL_OK;
}
/**
* @brief Handle WWDG interrupt request.
* @note The Early Wakeup Interrupt (EWI) can be used if specific safety operations
* or data logging must be performed before the actual reset is generated.
* The EWI interrupt is enabled by calling HAL_WWDG_Init function with
* EWIMode set to WWDG_EWI_ENABLE.
* When the downcounter reaches the value 0x40, and EWI interrupt is
* generated and the corresponding Interrupt Service Routine (ISR) can
* be used to trigger specific actions (such as communications or data
* logging), before resetting the device.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval None
*/
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
{
/* Check if Early Wakeup Interrupt is enable */
if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET)
{
/* Check if WWDG Early Wakeup Interrupt occurred */
if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
{
/* Clear the WWDG Early Wakeup flag */
__HAL_WWDG_CLEAR_FLAG(hwwdg, WWDG_FLAG_EWIF);
/* Early Wakeup callback */
HAL_WWDG_EarlyWakeupCallback(hwwdg);
}
}
}
/**
* @brief WWDG Early Wakeup callback.
* @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains
* the configuration information for the specified WWDG module.
* @retval None
*/
__weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef* hwwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hwwdg);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_WWDG_EarlyWakeupCallback could be implemented in the user file
*/
}
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_WWDG_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_adc.c
Executable
+920
View File
@@ -0,0 +1,920 @@
/**
******************************************************************************
* @file stm32f7xx_ll_adc.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief ADC LL module driver
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_adc.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (ADC1) || defined (ADC2) || defined (ADC3)
/** @addtogroup ADC_LL ADC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup ADC_LL_Private_Macros
* @{
*/
/* Check of parameters for configuration of ADC hierarchical scope: */
/* common to several ADC instances. */
#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
|| ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC instance. */
#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
|| ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
)
#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
|| ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
)
#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
|| ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
)
#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
|| ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group regular */
#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
|| ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
)
#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
|| ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
)
#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
|| ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
)
#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
|| ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
|| ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
)
#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
|| ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* ADC group injected */
#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
|| ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
)
#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
|| ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
)
#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
|| ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
|| ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
)
#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
|| ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
)
/* Check of parameters for configuration of ADC hierarchical scope: */
/* multimode. */
#if defined(ADC3)
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
)
#else
#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
|| ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
)
#endif
#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
|| ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
)
#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
|| ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
)
#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
|| ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
)
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_LL_Exported_Functions
* @{
*/
/** @addtogroup ADC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize registers of all ADC instances belonging to
* the same ADC common instance to their default reset values.
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC common registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
{
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
/* Force reset of ADC clock (core clock) */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
/* Release reset of ADC clock (core clock) */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
return SUCCESS;
}
/**
* @brief Initialize some features of ADC common parameters
* (all ADC instances belonging to the same ADC common instance)
* and multimode (for devices with several ADC instances available).
* @note The setting of ADC common parameters is conditioned to
* ADC instances state:
* All ADC instances belonging to the same ADC common instance
* must be disabled.
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC common registers are initialized
* - ERROR: ADC common registers are not initialized
*/
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
{
assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
}
/* Note: Hardware constraint (refer to description of functions */
/* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
/* On this STM32 serie, setting of these features is conditioned to */
/* ADC state: */
/* All ADC instances of the ADC common group must be disabled. */
if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - common to several ADC */
/* (all ADC instances belonging to the same ADC common instance) */
/* - Set ADC clock (conversion clock) */
/* - multimode (if several ADC instances available on the */
/* selected device) */
/* - Set ADC multimode configuration */
/* - Set ADC multimode DMA transfer */
/* - Set ADC multimode: delay between 2 sampling phases */
if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
{
MODIFY_REG(ADCxy_COMMON->CCR,
ADC_CCR_ADCPRE
| ADC_CCR_MULTI
| ADC_CCR_DMA
| ADC_CCR_DDS
| ADC_CCR_DELAY
,
ADC_CommonInitStruct->CommonClock
| ADC_CommonInitStruct->Multimode
| ADC_CommonInitStruct->MultiDMATransfer
| ADC_CommonInitStruct->MultiTwoSamplingDelay
);
}
else
{
MODIFY_REG(ADCxy_COMMON->CCR,
ADC_CCR_ADCPRE
| ADC_CCR_MULTI
| ADC_CCR_DMA
| ADC_CCR_DDS
| ADC_CCR_DELAY
,
ADC_CommonInitStruct->CommonClock
| LL_ADC_MULTI_INDEPENDENT
);
}
}
else
{
/* Initialization error: One or several ADC instances belonging to */
/* the same ADC common instance are not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
* @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
{
/* Set ADC_CommonInitStruct fields to default values */
/* Set fields of ADC common */
/* (all ADC instances belonging to the same ADC common instance) */
ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
/* Set fields of ADC multimode */
ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
}
/**
* @brief De-initialize registers of the selected ADC instance
* to their default reset values.
* @note To reset all ADC instances quickly (perform a hard reset),
* use function @ref LL_ADC_CommonDeInit().
* @param ADCx ADC instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are de-initialized
* - ERROR: ADC registers are not de-initialized
*/
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
/* Disable ADC instance if not already disabled. */
if(LL_ADC_IsEnabled(ADCx) == 1U)
{
/* Set ADC group regular trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
/* Set ADC group injected trigger source to SW start to ensure to not */
/* have an external trigger event occurring during the conversion stop */
/* ADC disable process. */
LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
/* Disable the ADC instance */
LL_ADC_Disable(ADCx);
}
/* Check whether ADC state is compliant with expected state */
/* (hardware requirements of bits state to reset registers below) */
if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
{
/* ========== Reset ADC registers ========== */
/* Reset register SR */
CLEAR_BIT(ADCx->SR,
( LL_ADC_FLAG_STRT
| LL_ADC_FLAG_JSTRT
| LL_ADC_FLAG_EOCS
| LL_ADC_FLAG_OVR
| LL_ADC_FLAG_JEOS
| LL_ADC_FLAG_AWD1 )
);
/* Reset register CR1 */
CLEAR_BIT(ADCx->CR1,
( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
| ADC_CR1_JAWDEN
| ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
| ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
| ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
| ADC_CR1_AWDCH )
);
/* Reset register CR2 */
CLEAR_BIT(ADCx->CR2,
( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
| ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
| ADC_CR2_ALIGN | ADC_CR2_EOCS
| ADC_CR2_DDS | ADC_CR2_DMA
| ADC_CR2_CONT | ADC_CR2_ADON )
);
/* Reset register SMPR1 */
CLEAR_BIT(ADCx->SMPR1,
( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
| ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
| ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
);
/* Reset register SMPR2 */
CLEAR_BIT(ADCx->SMPR2,
( ADC_SMPR2_SMP9
| ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
| ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
| ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
);
/* Reset register JOFR1 */
CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
/* Reset register JOFR2 */
CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
/* Reset register JOFR3 */
CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
/* Reset register JOFR4 */
CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
/* Reset register HTR */
SET_BIT(ADCx->HTR, ADC_HTR_HT);
/* Reset register LTR */
CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
/* Reset register SQR1 */
CLEAR_BIT(ADCx->SQR1,
( ADC_SQR1_L
| ADC_SQR1_SQ16
| ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
);
/* Reset register SQR2 */
CLEAR_BIT(ADCx->SQR2,
( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
| ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
);
/* Reset register JSQR */
CLEAR_BIT(ADCx->JSQR,
( ADC_JSQR_JL
| ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
| ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
);
/* Reset register DR */
/* bits in access mode read only, no direct reset applicable */
/* Reset registers JDR1, JDR2, JDR3, JDR4 */
/* bits in access mode read only, no direct reset applicable */
/* Reset register CCR */
CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
}
return status;
}
/**
* @brief Initialize some features of ADC instance.
* @note These parameters have an impact on ADC scope: ADC instance.
* Affects both group regular and group injected (availability
* of ADC group injected depends on STM32 families).
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Instance .
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, some other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group regular or group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC instance */
/* - Set ADC data resolution */
/* - Set ADC conversion data alignment */
MODIFY_REG(ADCx->CR1,
ADC_CR1_RES
| ADC_CR1_SCAN
,
ADC_InitStruct->Resolution
| ADC_InitStruct->SequencersScanMode
);
MODIFY_REG(ADCx->CR2,
ADC_CR2_ALIGN
,
ADC_InitStruct->DataAlignment
);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_InitTypeDef field to default value.
* @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
{
/* Set ADC_InitStruct fields to default values */
/* Set fields of ADC instance */
ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
/* Enable scan mode to have a generic behavior with ADC of other */
/* STM32 families, without this setting available: */
/* ADC group regular sequencer and ADC group injected sequencer depend */
/* only of their own configuration. */
ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
}
/**
* @brief Initialize some features of ADC group regular.
* @note These parameters have an impact on ADC scope: ADC group regular.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "REG").
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group regular or group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_REG_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
}
assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC group regular */
/* - Set ADC group regular trigger source */
/* - Set ADC group regular sequencer length */
/* - Set ADC group regular sequencer discontinuous mode */
/* - Set ADC group regular continuous mode */
/* - Set ADC group regular conversion data transfer: no transfer or */
/* transfer by DMA, and DMA requests mode */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
ADC_REG_InitStruct->SequencerLength
| ADC_REG_InitStruct->SequencerDiscont
);
}
else
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_DISCEN
| ADC_CR1_DISCNUM
,
ADC_REG_InitStruct->SequencerLength
| LL_ADC_REG_SEQ_DISCONT_DISABLE
);
}
MODIFY_REG(ADCx->CR2,
ADC_CR2_EXTSEL
| ADC_CR2_EXTEN
| ADC_CR2_CONT
| ADC_CR2_DMA
| ADC_CR2_DDS
,
(ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
| ADC_REG_InitStruct->ContinuousMode
| ADC_REG_InitStruct->DMATransfer
);
/* Set ADC group regular sequencer length and scan direction */
/* Note: Hardware constraint (refer to description of this function): */
/* Note: If ADC instance feature scan mode is disabled */
/* (refer to ADC instance initialization structure */
/* parameter @ref SequencersScanMode */
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
/* this parameter is discarded. */
LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
* @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
{
/* Set ADC_REG_InitStruct fields to default values */
/* Set fields of ADC group regular */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
}
/**
* @brief Initialize some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "INJ").
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
* @note After using this function, other features must be configured
* using LL unitary functions.
* The minimum configuration remaining to be done is:
* - Set ADC group injected sequencer:
* map channel on the selected sequencer rank.
* Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
* - Set ADC channel sampling time
* Refer to function LL_ADC_SetChannelSamplingTime();
* @param ADCx ADC instance
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ADC registers are initialized
* - ERROR: ADC registers are not initialized
*/
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(ADCx));
assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
{
assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
}
assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
/* Note: Hardware constraint (refer to description of this function): */
/* ADC instance must be disabled. */
if(LL_ADC_IsEnabled(ADCx) == 0U)
{
/* Configuration of ADC hierarchical scope: */
/* - ADC group injected */
/* - Set ADC group injected trigger source */
/* - Set ADC group injected sequencer length */
/* - Set ADC group injected sequencer discontinuous mode */
/* - Set ADC group injected conversion trigger: independent or */
/* from ADC group regular */
/* Note: On this STM32 serie, ADC trigger edge is set when starting */
/* ADC conversion. */
/* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_JDISCEN
| ADC_CR1_JAUTO
,
ADC_INJ_InitStruct->SequencerDiscont
| ADC_INJ_InitStruct->TrigAuto
);
}
else
{
MODIFY_REG(ADCx->CR1,
ADC_CR1_JDISCEN
| ADC_CR1_JAUTO
,
LL_ADC_REG_SEQ_DISCONT_DISABLE
| ADC_INJ_InitStruct->TrigAuto
);
}
MODIFY_REG(ADCx->CR2,
ADC_CR2_JEXTSEL
| ADC_CR2_JEXTEN
,
(ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
);
/* Note: Hardware constraint (refer to description of this function): */
/* Note: If ADC instance feature scan mode is disabled */
/* (refer to ADC instance initialization structure */
/* parameter @ref SequencersScanMode */
/* or function @ref LL_ADC_SetSequencersScanMode() ), */
/* this parameter is discarded. */
LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
}
else
{
/* Initialization error: ADC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
* @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
{
/* Set ADC_INJ_InitStruct fields to default values */
/* Set fields of ADC group injected */
ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ADC1 || ADC2 || ADC3 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_crc.c
Executable
+125
View File
@@ -0,0 +1,125 @@
/**
******************************************************************************
* @file stm32f7xx_ll_crc.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief CRC LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_crc.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (CRC)
/** @addtogroup CRC_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRC_LL_Exported_Functions
* @{
*/
/** @addtogroup CRC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize CRC registers (Registers restored to their default values).
* @param CRCx CRC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: CRC registers are de-initialized
* - ERROR: CRC registers are not de-initialized
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_CRC_ALL_INSTANCE(CRCx));
if (CRCx == CRC)
{
/* Force CRC reset */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_CRC);
/* Release CRC reset */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_CRC);
}
else
{
status = ERROR;
}
return (status);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (CRC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dac.c
Executable
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@@ -0,0 +1,273 @@
/**
******************************************************************************
* @file stm32f7xx_ll_dac.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief DAC LL module driver
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_dac.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined(DAC)
/** @addtogroup DAC_LL DAC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DAC_LL_Private_Macros
* @{
*/
#define IS_LL_DAC_CHANNEL(__DACX__, __DAC_CHANNEL__) \
( \
((__DAC_CHANNEL__) == LL_DAC_CHANNEL_1) \
|| ((__DAC_CHANNEL__) == LL_DAC_CHANNEL_2) \
)
#define IS_LL_DAC_TRIGGER_SOURCE(__TRIGGER_SOURCE__) \
( ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_SOFTWARE) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM2_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM4_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM5_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM6_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM7_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_TIM8_TRGO) \
|| ((__TRIGGER_SOURCE__) == LL_DAC_TRIG_EXT_EXTI_LINE9) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_MODE(__WAVE_AUTO_GENERATION_MODE__) \
( ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NONE) \
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_NOISE) \
|| ((__WAVE_AUTO_GENERATION_MODE__) == LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) \
)
#define IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(__WAVE_AUTO_GENERATION_CONFIG__) \
( ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BIT0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS1_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS2_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS3_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS4_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS5_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS6_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS7_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS8_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS9_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS10_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_NOISE_LFSR_UNMASK_BITS11_0) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_3) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_7) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_15) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_31) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_63) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_127) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_255) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_511) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_1023) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_2047) \
|| ((__WAVE_AUTO_GENERATION_CONFIG__) == LL_DAC_TRIANGLE_AMPLITUDE_4095) \
)
#define IS_LL_DAC_OUTPUT_BUFFER(__OUTPUT_BUFFER__) \
( ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_ENABLE) \
|| ((__OUTPUT_BUFFER__) == LL_DAC_OUTPUT_BUFFER_DISABLE) \
)
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_LL_Exported_Functions
* @{
*/
/** @addtogroup DAC_LL_EF_Init
* @{
*/
/**
* @brief De-initialize registers of the selected DAC instance
* to their default reset values.
* @param DACx DAC instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DAC registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx)
{
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(DACx));
/* Force reset of DAC1 clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_DAC1);
/* Release reset of DAC1 clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_DAC1);
return SUCCESS;
}
/**
* @brief Initialize some features of DAC instance.
* @note The setting of these parameters by function @ref LL_DAC_Init()
* is conditioned to DAC state:
* DAC instance must be disabled.
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2
* @param DAC_InitStruct Pointer to a @ref LL_DAC_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DAC registers are initialized
* - ERROR: DAC registers are not initialized
*/
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(DACx));
assert_param(IS_LL_DAC_CHANNEL(DACx, DAC_Channel));
assert_param(IS_LL_DAC_TRIGGER_SOURCE(DAC_InitStruct->TriggerSource));
assert_param(IS_LL_DAC_OUTPUT_BUFFER(DAC_InitStruct->OutputBuffer));
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_MODE(DAC_InitStruct->WaveAutoGeneration));
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
{
assert_param(IS_LL_DAC_WAVE_AUTO_GENER_CONFIG(DAC_InitStruct->WaveAutoGenerationConfig));
}
/* Note: Hardware constraint (refer to description of this function) */
/* DAC instance must be disabled. */
if(LL_DAC_IsEnabled(DACx, DAC_Channel) == 0U)
{
/* Configuration of DAC channel: */
/* - TriggerSource */
/* - WaveAutoGeneration */
/* - OutputBuffer */
if (DAC_InitStruct->WaveAutoGeneration != LL_DAC_WAVE_AUTO_GENERATION_NONE)
{
MODIFY_REG(DACx->CR,
( DAC_CR_TSEL1
| DAC_CR_WAVE1
| DAC_CR_MAMP1
| DAC_CR_BOFF1
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
,
( DAC_InitStruct->TriggerSource
| DAC_InitStruct->WaveAutoGeneration
| DAC_InitStruct->WaveAutoGenerationConfig
| DAC_InitStruct->OutputBuffer
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
else
{
MODIFY_REG(DACx->CR,
( DAC_CR_TSEL1
| DAC_CR_WAVE1
| DAC_CR_BOFF1
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
,
( DAC_InitStruct->TriggerSource
| LL_DAC_WAVE_AUTO_GENERATION_NONE
| DAC_InitStruct->OutputBuffer
) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
}
else
{
/* Initialization error: DAC instance is not disabled. */
status = ERROR;
}
return status;
}
/**
* @brief Set each @ref LL_DAC_InitTypeDef field to default value.
* @param DAC_InitStruct pointer to a @ref LL_DAC_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct)
{
/* Set DAC_InitStruct fields to default values */
DAC_InitStruct->TriggerSource = LL_DAC_TRIG_SOFTWARE;
DAC_InitStruct->WaveAutoGeneration = LL_DAC_WAVE_AUTO_GENERATION_NONE;
/* Note: Parameter discarded if wave auto generation is disabled, */
/* set anyway to its default value. */
DAC_InitStruct->WaveAutoGenerationConfig = LL_DAC_NOISE_LFSR_UNMASK_BIT0;
DAC_InitStruct->OutputBuffer = LL_DAC_OUTPUT_BUFFER_ENABLE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DAC */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma.c
Executable
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/**
******************************************************************************
* @file stm32f7xx_ll_dma.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief DMA LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_dma.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (DMA1) || defined (DMA2)
/** @defgroup DMA_LL DMA
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DMA_LL_Private_Macros
* @{
*/
#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
((__VALUE__) == LL_DMA_MODE_PFCTRL))
#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#if defined(DMA_CHANNEL_SELECTION_8_15)
#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
((__VALUE__) == LL_DMA_CHANNEL_1) || \
((__VALUE__) == LL_DMA_CHANNEL_2) || \
((__VALUE__) == LL_DMA_CHANNEL_3) || \
((__VALUE__) == LL_DMA_CHANNEL_4) || \
((__VALUE__) == LL_DMA_CHANNEL_5) || \
((__VALUE__) == LL_DMA_CHANNEL_6) || \
((__VALUE__) == LL_DMA_CHANNEL_7) || \
((__VALUE__) == LL_DMA_CHANNEL_8) || \
((__VALUE__) == LL_DMA_CHANNEL_9) || \
((__VALUE__) == LL_DMA_CHANNEL_10) || \
((__VALUE__) == LL_DMA_CHANNEL_11) || \
((__VALUE__) == LL_DMA_CHANNEL_12) || \
((__VALUE__) == LL_DMA_CHANNEL_13) || \
((__VALUE__) == LL_DMA_CHANNEL_14) || \
((__VALUE__) == LL_DMA_CHANNEL_15))
#else
#define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
((__VALUE__) == LL_DMA_CHANNEL_1) || \
((__VALUE__) == LL_DMA_CHANNEL_2) || \
((__VALUE__) == LL_DMA_CHANNEL_3) || \
((__VALUE__) == LL_DMA_CHANNEL_4) || \
((__VALUE__) == LL_DMA_CHANNEL_5) || \
((__VALUE__) == LL_DMA_CHANNEL_6) || \
((__VALUE__) == LL_DMA_CHANNEL_7))
#endif /* DMA_CHANNEL_SELECTION_8_15 */
#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
#define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
(((STREAM) == LL_DMA_STREAM_0) || \
((STREAM) == LL_DMA_STREAM_1) || \
((STREAM) == LL_DMA_STREAM_2) || \
((STREAM) == LL_DMA_STREAM_3) || \
((STREAM) == LL_DMA_STREAM_4) || \
((STREAM) == LL_DMA_STREAM_5) || \
((STREAM) == LL_DMA_STREAM_6) || \
((STREAM) == LL_DMA_STREAM_7) || \
((STREAM) == LL_DMA_STREAM_ALL))) ||\
(((INSTANCE) == DMA2) && \
(((STREAM) == LL_DMA_STREAM_0) || \
((STREAM) == LL_DMA_STREAM_1) || \
((STREAM) == LL_DMA_STREAM_2) || \
((STREAM) == LL_DMA_STREAM_3) || \
((STREAM) == LL_DMA_STREAM_4) || \
((STREAM) == LL_DMA_STREAM_5) || \
((STREAM) == LL_DMA_STREAM_6) || \
((STREAM) == LL_DMA_STREAM_7) || \
((STREAM) == LL_DMA_STREAM_ALL))))
#define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
((STATE) == LL_DMA_FIFOMODE_ENABLE))
#define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
#define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
((BURST) == LL_DMA_MBURST_INC4) || \
((BURST) == LL_DMA_MBURST_INC8) || \
((BURST) == LL_DMA_MBURST_INC16))
#define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
((BURST) == LL_DMA_PBURST_INC4) || \
((BURST) == LL_DMA_PBURST_INC8) || \
((BURST) == LL_DMA_PBURST_INC16))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_LL_Exported_Functions
* @{
*/
/** @addtogroup DMA_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the DMA registers to their default reset values.
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @arg @ref LL_DMA_STREAM_ALL
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are de-initialized
* - ERROR: DMA registers are not de-initialized
*/
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
{
DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
ErrorStatus status = SUCCESS;
/* Check the DMA Instance DMAx and Stream parameters*/
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
if (Stream == LL_DMA_STREAM_ALL)
{
if (DMAx == DMA1)
{
/* Force reset of DMA clock */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
/* Release reset of DMA clock */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
}
else if (DMAx == DMA2)
{
/* Force reset of DMA clock */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
/* Release reset of DMA clock */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
}
else
{
status = ERROR;
}
}
else
{
/* Disable the selected Stream */
LL_DMA_DisableStream(DMAx,Stream);
/* Get the DMA Stream Instance */
tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
/* Reset DMAx_Streamy configuration register */
LL_DMA_WriteReg(tmp, CR, 0U);
/* Reset DMAx_Streamy remaining bytes register */
LL_DMA_WriteReg(tmp, NDTR, 0U);
/* Reset DMAx_Streamy peripheral address register */
LL_DMA_WriteReg(tmp, PAR, 0U);
/* Reset DMAx_Streamy memory address register */
LL_DMA_WriteReg(tmp, M0AR, 0U);
/* Reset DMAx_Streamy memory address register */
LL_DMA_WriteReg(tmp, M1AR, 0U);
/* Reset DMAx_Streamy FIFO control register */
LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
/* Reset Channel register field for DMAx Stream*/
LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
if(Stream == LL_DMA_STREAM_0)
{
/* Reset the Stream0 pending flags */
DMAx->LIFCR = 0x0000003FU;
}
else if(Stream == LL_DMA_STREAM_1)
{
/* Reset the Stream1 pending flags */
DMAx->LIFCR = 0x00000F40U;
}
else if(Stream == LL_DMA_STREAM_2)
{
/* Reset the Stream2 pending flags */
DMAx->LIFCR = 0x003F0000U;
}
else if(Stream == LL_DMA_STREAM_3)
{
/* Reset the Stream3 pending flags */
DMAx->LIFCR = 0x0F400000U;
}
else if(Stream == LL_DMA_STREAM_4)
{
/* Reset the Stream4 pending flags */
DMAx->HIFCR = 0x0000003FU;
}
else if(Stream == LL_DMA_STREAM_5)
{
/* Reset the Stream5 pending flags */
DMAx->HIFCR = 0x00000F40U;
}
else if(Stream == LL_DMA_STREAM_6)
{
/* Reset the Stream6 pending flags */
DMAx->HIFCR = 0x003F0000U;
}
else if(Stream == LL_DMA_STREAM_7)
{
/* Reset the Stream7 pending flags */
DMAx->HIFCR = 0x0F400000U;
}
else
{
status = ERROR;
}
}
return status;
}
/**
* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
* @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
* @arg @ref __LL_DMA_GET_INSTANCE
* @arg @ref __LL_DMA_GET_STREAM
* @param DMAx DMAx Instance
* @param Stream This parameter can be one of the following values:
* @arg @ref LL_DMA_STREAM_0
* @arg @ref LL_DMA_STREAM_1
* @arg @ref LL_DMA_STREAM_2
* @arg @ref LL_DMA_STREAM_3
* @arg @ref LL_DMA_STREAM_4
* @arg @ref LL_DMA_STREAM_5
* @arg @ref LL_DMA_STREAM_6
* @arg @ref LL_DMA_STREAM_7
* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA registers are initialized
* - ERROR: Not applicable
*/
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Check the DMA Instance DMAx and Stream parameters*/
assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
/* Check the DMA parameters from DMA_InitStruct */
assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
/* Check the memory burst, peripheral burst and FIFO threshold parameters only
when FIFO mode is enabled */
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
{
assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
}
/*---------------------------- DMAx SxCR Configuration ------------------------
* Configure DMAx_Streamy: data transfer direction, data transfer mode,
* peripheral and memory increment mode,
* data size alignment and priority level with parameters :
* - Direction: DMA_SxCR_DIR[1:0] bits
* - Mode: DMA_SxCR_CIRC bit
* - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
* - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
* - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
* - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
* - Priority: DMA_SxCR_PL[1:0] bits
*/
LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
DMA_InitStruct->Mode | \
DMA_InitStruct->PeriphOrM2MSrcIncMode | \
DMA_InitStruct->MemoryOrM2MDstIncMode | \
DMA_InitStruct->PeriphOrM2MSrcDataSize | \
DMA_InitStruct->MemoryOrM2MDstDataSize | \
DMA_InitStruct->Priority
);
if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
{
/*---------------------------- DMAx SxFCR Configuration ------------------------
* Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
* - FIFOMode: DMA_SxFCR_DMDIS bit
* - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
*/
LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
/*---------------------------- DMAx SxCR Configuration --------------------------
* Configure DMAx_Streamy: memory burst transfer with parameters :
* - MemBurst: DMA_SxCR_MBURST[1:0] bits
*/
LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
/*---------------------------- DMAx SxCR Configuration --------------------------
* Configure DMAx_Streamy: peripheral burst transfer with parameters :
* - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
*/
LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
}
/*-------------------------- DMAx SxM0AR Configuration --------------------------
* Configure the memory or destination base address with parameter :
* - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
*/
LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
/*-------------------------- DMAx SxPAR Configuration ---------------------------
* Configure the peripheral or source base address with parameter :
* - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
*/
LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
/*--------------------------- DMAx SxNDTR Configuration -------------------------
* Configure the peripheral base address with parameter :
* - NbData: DMA_SxNDT[15:0] bits
*/
LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
/*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
* Configure the peripheral base address with parameter :
* - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits
*/
LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
return SUCCESS;
}
/**
* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
* @retval None
*/
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
{
/* Set DMA_InitStruct fields to default values */
DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
DMA_InitStruct->NbData = 0x00000000U;
DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMA1 || DMA2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_dma2d.c
Executable
+653
View File
@@ -0,0 +1,653 @@
/**
******************************************************************************
* @file stm32f7xx_ll_dma2d.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief DMA2D LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_dma2d.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (DMA2D)
/** @addtogroup DMA2D_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA2D_LL_Private_Constants DMA2D Private Constants
* @{
*/
#define LL_DMA2D_COLOR 0xFFU /*!< Maximum output color setting */
#define LL_DMA2D_NUMBEROFLINES DMA2D_NLR_NL /*!< Maximum number of lines */
#define LL_DMA2D_NUMBEROFPIXELS (DMA2D_NLR_PL >> DMA2D_NLR_PL_Pos) /*!< Maximum number of pixels per lines */
#define LL_DMA2D_OFFSET_MAX 0x3FFFU /*!< Maximum output line offset expressed in pixels */
#define LL_DMA2D_CLUTSIZE_MAX 0xFFU /*!< Maximum CLUT size */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup DMA2D_LL_Private_Macros
* @{
*/
#define IS_LL_DMA2D_MODE(MODE) (((MODE) == LL_DMA2D_MODE_M2M) || \
((MODE) == LL_DMA2D_MODE_M2M_PFC) || \
((MODE) == LL_DMA2D_MODE_M2M_BLEND) || \
((MODE) == LL_DMA2D_MODE_R2M))
#define IS_LL_DMA2D_OCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB8888) || \
((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB888) || \
((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_RGB565) || \
((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB1555) || \
((MODE_ARGB) == LL_DMA2D_OUTPUT_MODE_ARGB4444))
#define IS_LL_DMA2D_GREEN(GREEN) ((GREEN) <= LL_DMA2D_COLOR)
#define IS_LL_DMA2D_RED(RED) ((RED) <= LL_DMA2D_COLOR)
#define IS_LL_DMA2D_BLUE(BLUE) ((BLUE) <= LL_DMA2D_COLOR)
#define IS_LL_DMA2D_ALPHA(ALPHA) ((ALPHA) <= LL_DMA2D_COLOR)
#define IS_LL_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= LL_DMA2D_OFFSET_MAX)
#define IS_LL_DMA2D_LINE(LINES) ((LINES) <= LL_DMA2D_NUMBEROFLINES)
#define IS_LL_DMA2D_PIXEL(PIXELS) ((PIXELS) <= LL_DMA2D_NUMBEROFPIXELS)
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
#define IS_LL_DMA2D_ALPHAINV(ALPHA) (((ALPHA) == LL_DMA2D_ALPHA_REGULAR) || \
((ALPHA) == LL_DMA2D_ALPHA_INVERTED))
#define IS_LL_DMA2D_RBSWAP(RBSWAP) (((RBSWAP) == LL_DMA2D_RB_MODE_REGULAR) || \
((RBSWAP) == LL_DMA2D_RB_MODE_SWAP))
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
#define IS_LL_DMA2D_LCMODE(MODE_ARGB) (((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB8888) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB888) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_RGB565) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB1555) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_ARGB4444) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L8) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL44) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_AL88) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_L4) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A8) || \
((MODE_ARGB) == LL_DMA2D_INPUT_MODE_A4))
#define IS_LL_DMA2D_CLUTCMODE(CLUTCMODE) (((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_ARGB8888) || \
((CLUTCMODE) == LL_DMA2D_CLUT_COLOR_MODE_RGB888))
#define IS_LL_DMA2D_CLUTSIZE(SIZE) ((SIZE) <= LL_DMA2D_CLUTSIZE_MAX)
#define IS_LL_DMA2D_ALPHAMODE(MODE) (((MODE) == LL_DMA2D_ALPHA_MODE_NO_MODIF) || \
((MODE) == LL_DMA2D_ALPHA_MODE_REPLACE) || \
((MODE) == LL_DMA2D_ALPHA_MODE_COMBINE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA2D_LL_Exported_Functions
* @{
*/
/** @addtogroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
* @{
*/
/**
* @brief De-initialize DMA2D registers (registers restored to their default values).
* @param DMA2Dx DMA2D Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA2D registers are de-initialized
* - ERROR: DMA2D registers are not de-initialized
*/
ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
if (DMA2Dx == DMA2D)
{
/* Force reset of DMA2D clock */
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2D);
/* Release reset of DMA2D clock */
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2D);
}
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize DMA2D registers according to the specified parameters in DMA2D_InitStruct.
* @note DMA2D transfers must be disabled to set initialization bits in configuration registers,
* otherwise ERROR result is returned.
* @param DMA2Dx DMA2D Instance
* @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure
* that contains the configuration information for the specified DMA2D peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content
* - ERROR: Issue occurred during DMA2D registers initialization
*/
ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
{
ErrorStatus status = ERROR;
LL_DMA2D_ColorTypeDef DMA2D_ColorStruct;
uint32_t tmp = 0U, tmp1 = 0U, tmp2 = 0U;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
assert_param(IS_LL_DMA2D_MODE(DMA2D_InitStruct->Mode));
assert_param(IS_LL_DMA2D_OCMODE(DMA2D_InitStruct->ColorMode));
assert_param(IS_LL_DMA2D_GREEN(DMA2D_InitStruct->OutputGreen));
assert_param(IS_LL_DMA2D_RED(DMA2D_InitStruct->OutputRed));
assert_param(IS_LL_DMA2D_BLUE(DMA2D_InitStruct->OutputBlue));
assert_param(IS_LL_DMA2D_ALPHA(DMA2D_InitStruct->OutputAlpha));
assert_param(IS_LL_DMA2D_OFFSET(DMA2D_InitStruct->LineOffset));
assert_param(IS_LL_DMA2D_LINE(DMA2D_InitStruct->NbrOfLines));
assert_param(IS_LL_DMA2D_PIXEL(DMA2D_InitStruct->NbrOfPixelsPerLines));
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_InitStruct->AlphaInversionMode));
assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_InitStruct->RBSwapMode));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* DMA2D transfers must be disabled to configure bits in initialization registers */
tmp = LL_DMA2D_IsTransferOngoing(DMA2Dx);
tmp1 = LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2Dx);
tmp2 = LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2Dx);
if ((tmp == 0U) && (tmp1 == 0U) && (tmp2 == 0U))
{
/* DMA2D CR register configuration -------------------------------------------*/
LL_DMA2D_SetMode(DMA2Dx, DMA2D_InitStruct->Mode);
/* DMA2D OPFCCR register configuration ---------------------------------------*/
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
MODIFY_REG(DMA2Dx->OPFCCR, (DMA2D_OPFCCR_CM | DMA2D_OPFCCR_RBS | DMA2D_OPFCCR_AI), \
(DMA2D_InitStruct->ColorMode | DMA2D_InitStruct->AlphaInversionMode | DMA2D_InitStruct->RBSwapMode));
#else
MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, DMA2D_InitStruct->ColorMode);
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* DMA2D OOR register configuration ------------------------------------------*/
LL_DMA2D_SetLineOffset(DMA2Dx, DMA2D_InitStruct->LineOffset);
/* DMA2D NLR register configuration ------------------------------------------*/
LL_DMA2D_ConfigSize(DMA2Dx, DMA2D_InitStruct->NbrOfLines, DMA2D_InitStruct->NbrOfPixelsPerLines);
/* DMA2D OMAR register configuration ------------------------------------------*/
LL_DMA2D_SetOutputMemAddr(DMA2Dx, DMA2D_InitStruct->OutputMemoryAddress);
/* DMA2D OCOLR register configuration ------------------------------------------*/
DMA2D_ColorStruct.ColorMode = DMA2D_InitStruct->ColorMode;
DMA2D_ColorStruct.OutputBlue = DMA2D_InitStruct->OutputBlue;
DMA2D_ColorStruct.OutputGreen = DMA2D_InitStruct->OutputGreen;
DMA2D_ColorStruct.OutputRed = DMA2D_InitStruct->OutputRed;
DMA2D_ColorStruct.OutputAlpha = DMA2D_InitStruct->OutputAlpha;
LL_DMA2D_ConfigOutputColor(DMA2Dx, &DMA2D_ColorStruct);
status = SUCCESS;
}
/* If DMA2D transfers are not disabled, return ERROR */
return (status);
}
/**
* @brief Set each @ref LL_DMA2D_InitTypeDef field to default value.
* @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct)
{
/* Set DMA2D_InitStruct fields to default values */
DMA2D_InitStruct->Mode = LL_DMA2D_MODE_M2M;
DMA2D_InitStruct->ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB8888;
DMA2D_InitStruct->LineOffset = 0x0U;
DMA2D_InitStruct->OutputBlue = 0x0U;
DMA2D_InitStruct->OutputGreen = 0x0U;
DMA2D_InitStruct->OutputRed = 0x0U;
DMA2D_InitStruct->OutputAlpha = 0x0U;
DMA2D_InitStruct->OutputMemoryAddress = 0x0U;
DMA2D_InitStruct->NbrOfLines = 0x0U;
DMA2D_InitStruct->NbrOfPixelsPerLines = 0x0U;
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
DMA2D_InitStruct->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
DMA2D_InitStruct->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR;
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
}
/**
* @brief Configure the foreground or background according to the specified parameters
* in the LL_DMA2D_LayerCfgTypeDef structure.
* @param DMA2Dx DMA2D Instance
* @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains
* the configuration information for the specified layer.
* @param LayerIdx: DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval None
*/
void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx)
{
/* Check the parameters */
assert_param(IS_LL_DMA2D_OFFSET(DMA2D_LayerCfg->LineOffset));
assert_param(IS_LL_DMA2D_LCMODE(DMA2D_LayerCfg->ColorMode));
assert_param(IS_LL_DMA2D_CLUTCMODE(DMA2D_LayerCfg->CLUTColorMode));
assert_param(IS_LL_DMA2D_CLUTSIZE(DMA2D_LayerCfg->CLUTSize));
assert_param(IS_LL_DMA2D_ALPHAMODE(DMA2D_LayerCfg->AlphaMode));
assert_param(IS_LL_DMA2D_GREEN(DMA2D_LayerCfg->Green));
assert_param(IS_LL_DMA2D_RED(DMA2D_LayerCfg->Red));
assert_param(IS_LL_DMA2D_BLUE(DMA2D_LayerCfg->Blue));
assert_param(IS_LL_DMA2D_ALPHA(DMA2D_LayerCfg->Alpha));
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
assert_param(IS_LL_DMA2D_ALPHAINV(DMA2D_LayerCfg->AlphaInversionMode));
assert_param(IS_LL_DMA2D_RBSWAP(DMA2D_LayerCfg->RBSwapMode));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
if (LayerIdx == 0U)
{
/* Configure the background memory address */
LL_DMA2D_BGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
/* Configure the background line offset */
LL_DMA2D_BGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
/* Configure the background Alpha value, Alpha mode, RB swap, Alpha inversion
CLUT size, CLUT Color mode and Color mode */
MODIFY_REG(DMA2Dx->BGPFCCR, \
(DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_RBS | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_AM | \
DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \
((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
(DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
DMA2D_LayerCfg->ColorMode));
#else
/* Configure the background Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */
MODIFY_REG(DMA2Dx->BGPFCCR, \
(DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM | DMA2D_BGPFCCR_CM), \
((DMA2D_LayerCfg->Alpha << DMA2D_BGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \
(DMA2D_LayerCfg->CLUTSize << DMA2D_BGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
DMA2D_LayerCfg->ColorMode));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Configure the background color */
LL_DMA2D_BGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
/* Configure the background CLUT memory address */
LL_DMA2D_BGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
}
else
{
/* Configure the foreground memory address */
LL_DMA2D_FGND_SetMemAddr(DMA2Dx, DMA2D_LayerCfg->MemoryAddress);
/* Configure the foreground line offset */
LL_DMA2D_FGND_SetLineOffset(DMA2Dx, DMA2D_LayerCfg->LineOffset);
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
/* Configure the foreground Alpha value, Alpha mode, RB swap, Alpha inversion
CLUT size, CLUT Color mode and Color mode */
MODIFY_REG(DMA2Dx->FGPFCCR, \
(DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_RBS | DMA2D_FGPFCCR_AI | DMA2D_FGPFCCR_AM | \
DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->RBSwapMode | \
DMA2D_LayerCfg->AlphaInversionMode | DMA2D_LayerCfg->AlphaMode | \
(DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
DMA2D_LayerCfg->ColorMode));
#else
/* Configure the foreground Alpha value, Alpha mode, CLUT size, CLUT Color mode and Color mode */
MODIFY_REG(DMA2Dx->FGPFCCR, \
(DMA2D_FGPFCCR_ALPHA | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM | DMA2D_FGPFCCR_CM), \
((DMA2D_LayerCfg->Alpha << DMA2D_FGPFCCR_ALPHA_Pos) | DMA2D_LayerCfg->AlphaMode | \
(DMA2D_LayerCfg->CLUTSize << DMA2D_FGPFCCR_CS_Pos) | DMA2D_LayerCfg->CLUTColorMode | \
DMA2D_LayerCfg->ColorMode));
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
/* Configure the foreground color */
LL_DMA2D_FGND_SetColor(DMA2Dx, DMA2D_LayerCfg->Red, DMA2D_LayerCfg->Green, DMA2D_LayerCfg->Blue);
/* Configure the foreground CLUT memory address */
LL_DMA2D_FGND_SetCLUTMemAddr(DMA2Dx, DMA2D_LayerCfg->CLUTMemoryAddress);
}
}
/**
* @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value.
* @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg)
{
/* Set DMA2D_LayerCfg fields to default values */
DMA2D_LayerCfg->MemoryAddress = 0x0U;
DMA2D_LayerCfg->ColorMode = LL_DMA2D_INPUT_MODE_ARGB8888;
DMA2D_LayerCfg->LineOffset = 0x0U;
DMA2D_LayerCfg->CLUTColorMode = LL_DMA2D_CLUT_COLOR_MODE_ARGB8888;
DMA2D_LayerCfg->CLUTSize = 0x0U;
DMA2D_LayerCfg->AlphaMode = LL_DMA2D_ALPHA_MODE_NO_MODIF;
DMA2D_LayerCfg->Alpha = 0x0U;
DMA2D_LayerCfg->Blue = 0x0U;
DMA2D_LayerCfg->Green = 0x0U;
DMA2D_LayerCfg->Red = 0x0U;
DMA2D_LayerCfg->CLUTMemoryAddress = 0x0U;
#if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
DMA2D_LayerCfg->AlphaInversionMode = LL_DMA2D_ALPHA_REGULAR;
DMA2D_LayerCfg->RBSwapMode = LL_DMA2D_RB_MODE_REGULAR;
#endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
}
/**
* @brief Initialize DMA2D output color register according to the specified parameters
* in DMA2D_ColorStruct.
* @param DMA2Dx DMA2D Instance
* @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains
* the color configuration information for the specified DMA2D peripheral.
* @retval None
*/
void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct)
{
uint32_t outgreen = 0U;
uint32_t outred = 0U;
uint32_t outalpha = 0U;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
assert_param(IS_LL_DMA2D_OCMODE(DMA2D_ColorStruct->ColorMode));
assert_param(IS_LL_DMA2D_GREEN(DMA2D_ColorStruct->OutputGreen));
assert_param(IS_LL_DMA2D_RED(DMA2D_ColorStruct->OutputRed));
assert_param(IS_LL_DMA2D_BLUE(DMA2D_ColorStruct->OutputBlue));
assert_param(IS_LL_DMA2D_ALPHA(DMA2D_ColorStruct->OutputAlpha));
/* DMA2D OCOLR register configuration ------------------------------------------*/
if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
{
outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
outred = DMA2D_ColorStruct->OutputRed << 16U;
outalpha = DMA2D_ColorStruct->OutputAlpha << 24U;
}
else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
{
outgreen = DMA2D_ColorStruct->OutputGreen << 8U;
outred = DMA2D_ColorStruct->OutputRed << 16U;
outalpha = 0x00000000U;
}
else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
{
outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
outred = DMA2D_ColorStruct->OutputRed << 11U;
outalpha = 0x00000000U;
}
else if (DMA2D_ColorStruct->ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
{
outgreen = DMA2D_ColorStruct->OutputGreen << 5U;
outred = DMA2D_ColorStruct->OutputRed << 10U;
outalpha = DMA2D_ColorStruct->OutputAlpha << 15U;
}
else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
{
outgreen = DMA2D_ColorStruct->OutputGreen << 4U;
outred = DMA2D_ColorStruct->OutputRed << 8U;
outalpha = DMA2D_ColorStruct->OutputAlpha << 12U;
}
LL_DMA2D_SetOutputColor(DMA2Dx, (outgreen | outred | DMA2D_ColorStruct->OutputBlue | outalpha));
}
/**
* @brief Return DMA2D output Blue color.
* @param DMA2Dx DMA2D Instance.
* @param ColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Blue color value between Min_Data=0 and Max_Data=0xFF
*/
uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color = 0U;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
/* DMA2D OCOLR register reading ------------------------------------------*/
if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFFU));
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x1FU));
}
else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFU));
}
return color;
}
/**
* @brief Return DMA2D output Green color.
* @param DMA2Dx DMA2D Instance.
* @param ColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Green color value between Min_Data=0 and Max_Data=0xFF
*/
uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color = 0U;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
/* DMA2D OCOLR register reading ------------------------------------------*/
if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF00U) >> 8U);
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7E0U) >> 5U);
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x3E0U) >> 5U);
}
else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF0U) >> 4U);
}
return color;
}
/**
* @brief Return DMA2D output Red color.
* @param DMA2Dx DMA2D Instance.
* @param ColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Red color value between Min_Data=0 and Max_Data=0xFF
*/
uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color = 0U;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
/* DMA2D OCOLR register reading ------------------------------------------*/
if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF0000U) >> 16U);
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF800U) >> 11U);
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x7C00U) >> 10U);
}
else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF00U) >> 8U);
}
return color;
}
/**
* @brief Return DMA2D output Alpha color.
* @param DMA2Dx DMA2D Instance.
* @param ColorMode This parameter can be one of the following values:
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
* @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
* @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
* @retval Output Alpha color value between Min_Data=0 and Max_Data=0xFF
*/
uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
{
uint32_t color = 0U;
/* Check the parameters */
assert_param(IS_DMA2D_ALL_INSTANCE(DMA2Dx));
assert_param(IS_LL_DMA2D_OCMODE(ColorMode));
/* DMA2D OCOLR register reading ------------------------------------------*/
if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB8888)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xFF000000U) >> 24U);
}
else if ((ColorMode == LL_DMA2D_OUTPUT_MODE_RGB888) || (ColorMode == LL_DMA2D_OUTPUT_MODE_RGB565))
{
color = 0x0U;
}
else if (ColorMode == LL_DMA2D_OUTPUT_MODE_ARGB1555)
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0x8000U) >> 15U);
}
else /* ColorMode = LL_DMA2D_OUTPUT_MODE_ARGB4444 */
{
color = (uint32_t)(READ_BIT(DMA2Dx->OCOLR, 0xF000U) >> 12U);
}
return color;
}
/**
* @brief Configure DMA2D transfer size.
* @param DMA2Dx DMA2D Instance
* @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
* @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
* @retval None
*/
void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines)
{
MODIFY_REG(DMA2Dx->NLR, (DMA2D_NLR_PL | DMA2D_NLR_NL), \
((NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos) | NbrOfLines));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (DMA2D) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_exti.c
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/**
******************************************************************************
* @file stm32f7xx_ll_exti.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief EXTI LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_exti.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup EXTI_LL_Private_Macros
* @{
*/
#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U)
#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \
|| ((__VALUE__) == LL_EXTI_MODE_EVENT) \
|| ((__VALUE__) == LL_EXTI_MODE_IT_EVENT))
#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \
|| ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup EXTI_LL_Exported_Functions
* @{
*/
/** @addtogroup EXTI_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the EXTI registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are de-initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_DeInit(void)
{
/* Interrupt mask register set to default reset values */
LL_EXTI_WriteReg(IMR, 0x00000000U);
/* Event mask register set to default reset values */
LL_EXTI_WriteReg(EMR, 0x00000000U);
/* Rising Trigger selection register set to default reset values */
LL_EXTI_WriteReg(RTSR, 0x00000000U);
/* Falling Trigger selection register set to default reset values */
LL_EXTI_WriteReg(FTSR, 0x00000000U);
/* Software interrupt event register set to default reset values */
LL_EXTI_WriteReg(SWIER, 0x00000000U);
/* Pending register set to default reset values */
LL_EXTI_WriteReg(PR, 0x01FFFFFFU);
return SUCCESS;
}
/**
* @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct.
* @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: EXTI registers are initialized
* - ERROR: not applicable
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31));
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand));
assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode));
/* ENABLE LineCommand */
if (EXTI_InitStruct->LineCommand != DISABLE)
{
assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger));
/* Configure EXTI Lines in range from 0 to 31 */
if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE)
{
switch (EXTI_InitStruct->Mode)
{
case LL_EXTI_MODE_IT:
/* First Disable Event on provided Lines */
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable IT on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_EVENT:
/* First Disable IT on provided Lines */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Event on provided Lines */
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_MODE_IT_EVENT:
/* Directly Enable IT & Event on provided Lines */
LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE)
{
switch (EXTI_InitStruct->Trigger)
{
case LL_EXTI_TRIGGER_RISING:
/* First Disable Falling Trigger on provided Lines */
LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Rising Trigger on provided Lines */
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_FALLING:
/* First Disable Rising Trigger on provided Lines */
LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
/* Then Enable Falling Trigger on provided Lines */
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
case LL_EXTI_TRIGGER_RISING_FALLING:
LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31);
break;
default:
status = ERROR;
break;
}
}
}
}
/* DISABLE LineCommand */
else
{
/* De-configure EXTI Lines in range from 0 to 31 */
LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31);
LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31);
}
return status;
}
/**
* @brief Set each @ref LL_EXTI_InitTypeDef field to default value.
* @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure.
* @retval None
*/
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE;
EXTI_InitStruct->LineCommand = DISABLE;
EXTI_InitStruct->Mode = LL_EXTI_MODE_IT;
EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (EXTI) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_fmc.c
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_gpio.c
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/**
******************************************************************************
* @file stm32f7xx_ll_gpio.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief GPIO LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_gpio.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
/** @addtogroup GPIO_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup GPIO_LL_Private_Macros
* @{
*/
#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL)))
#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\
((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\
((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\
((__VALUE__) == LL_GPIO_MODE_ANALOG))
#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\
((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN))
#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\
((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\
((__VALUE__) == LL_GPIO_PULL_UP) ||\
((__VALUE__) == LL_GPIO_PULL_DOWN))
#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\
((__VALUE__) == LL_GPIO_AF_1 ) ||\
((__VALUE__) == LL_GPIO_AF_2 ) ||\
((__VALUE__) == LL_GPIO_AF_3 ) ||\
((__VALUE__) == LL_GPIO_AF_4 ) ||\
((__VALUE__) == LL_GPIO_AF_5 ) ||\
((__VALUE__) == LL_GPIO_AF_6 ) ||\
((__VALUE__) == LL_GPIO_AF_7 ) ||\
((__VALUE__) == LL_GPIO_AF_8 ) ||\
((__VALUE__) == LL_GPIO_AF_9 ) ||\
((__VALUE__) == LL_GPIO_AF_10 ) ||\
((__VALUE__) == LL_GPIO_AF_11 ) ||\
((__VALUE__) == LL_GPIO_AF_12 ) ||\
((__VALUE__) == LL_GPIO_AF_13 ) ||\
((__VALUE__) == LL_GPIO_AF_14 ) ||\
((__VALUE__) == LL_GPIO_AF_15 ))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_LL_Exported_Functions
* @{
*/
/** @addtogroup GPIO_LL_EF_Init
* @{
*/
/**
* @brief De-initialize GPIO registers (Registers restored to their default values).
* @param GPIOx GPIO Port
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are de-initialized
* - ERROR: Wrong GPIO Port
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
/* Force and Release reset on clock of GPIOx Port */
if (GPIOx == GPIOA)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOA);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOA);
}
else if (GPIOx == GPIOB)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOB);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOB);
}
else if (GPIOx == GPIOC)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOC);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOC);
}
#if defined(GPIOD)
else if (GPIOx == GPIOD)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOD);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOD);
}
#endif /* GPIOD */
#if defined(GPIOE)
else if (GPIOx == GPIOE)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOE);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOE);
}
#endif /* GPIOE */
#if defined(GPIOF)
else if (GPIOx == GPIOF)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOF);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOF);
}
#endif /* GPIOF */
#if defined(GPIOG)
else if (GPIOx == GPIOG)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOG);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOG);
}
#endif /* GPIOG */
#if defined(GPIOH)
else if (GPIOx == GPIOH)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOH);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOH);
}
#endif /* GPIOH */
#if defined(GPIOI)
else if (GPIOx == GPIOI)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOI);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOI);
}
#endif /* GPIOI */
#if defined(GPIOJ)
else if (GPIOx == GPIOJ)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOJ);
}
#endif /* GPIOJ */
#if defined(GPIOK)
else if (GPIOx == GPIOK)
{
LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPIOK);
LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPIOK);
}
#endif /* GPIOK */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct.
* @param GPIOx GPIO Port
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
* that contains the configuration information for the specified GPIO peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content
* - ERROR: Not applicable
*/
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
uint32_t pinpos = 0x00000000U;
uint32_t currentpin = 0x00000000U;
/* Check the parameters */
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin));
assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode));
assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull));
/* ------------------------- Configure the port pins ---------------- */
/* Initialize pinpos on first pin set */
pinpos = POSITION_VAL(GPIO_InitStruct->Pin);
/* Configure the port pins */
while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00000000U)
{
/* Get current io position */
currentpin = (GPIO_InitStruct->Pin) & (0x00000001U << pinpos);
if (currentpin)
{
/* Pin Mode configuration */
LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode);
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Speed mode parameters */
assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed));
/* Speed mode configuration */
LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed);
}
/* Pull-up Pull down resistor configuration*/
LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull);
if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)
{
/* Check Alternate parameter */
assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate));
/* Speed mode configuration */
if (POSITION_VAL(currentpin) < 0x00000008U)
{
LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
else
{
LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate);
}
}
}
pinpos++;
}
if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE))
{
/* Check Output mode parameters */
assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType));
/* Output mode configuration*/
LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType);
}
return (SUCCESS);
}
/**
* @brief Set each @ref LL_GPIO_InitTypeDef field to default value.
* @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct)
{
/* Reset GPIO init structure parameters values */
GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL;
GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG;
GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL;
GPIO_InitStruct->Pull = LL_GPIO_PULL_NO;
GPIO_InitStruct->Alternate = LL_GPIO_AF_0;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_i2c.c
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/**
******************************************************************************
* @file stm32f7xx_ll_i2c.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief I2C LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_i2c.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
/** @defgroup I2C_LL I2C
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup I2C_LL_Private_Macros
* @{
*/
#define IS_LL_I2C_PERIPHERAL_MODE(__VALUE__) (((__VALUE__) == LL_I2C_MODE_I2C) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_HOST) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
#define IS_LL_I2C_ANALOG_FILTER(__VALUE__) (((__VALUE__) == LL_I2C_ANALOGFILTER_ENABLE) || \
((__VALUE__) == LL_I2C_ANALOGFILTER_DISABLE))
#define IS_LL_I2C_DIGITAL_FILTER(__VALUE__) ((__VALUE__) <= 0x0000000FU)
#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU)
#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \
((__VALUE__) == LL_I2C_NACK))
#define IS_LL_I2C_OWN_ADDRSIZE(__VALUE__) (((__VALUE__) == LL_I2C_OWNADDRESS1_7BIT) || \
((__VALUE__) == LL_I2C_OWNADDRESS1_10BIT))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_LL_Exported_Functions
* @{
*/
/** @addtogroup I2C_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the I2C registers to their default reset values.
* @param I2Cx I2C Instance.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: I2C registers are de-initialized
* - ERROR: I2C registers are not de-initialized
*/
uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx)
{
ErrorStatus status = SUCCESS;
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
if (I2Cx == I2C1)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1);
}
else if (I2Cx == I2C2)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C2);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C2);
}
else if (I2Cx == I2C3)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C3);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C3);
}
#if defined(I2C4)
else if (I2Cx == I2C4)
{
/* Force reset of I2C clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C4);
/* Release reset of I2C clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C4);
}
#endif
else
{
status = ERROR;
}
return status;
}
/**
* @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct.
* @param I2Cx I2C Instance.
* @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: I2C registers are initialized
* - ERROR: Not applicable
*/
uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Check the I2C Instance I2Cx */
assert_param(IS_I2C_ALL_INSTANCE(I2Cx));
/* Check the I2C parameters from I2C_InitStruct */
assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1));
assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge));
assert_param(IS_LL_I2C_OWN_ADDRSIZE(I2C_InitStruct->OwnAddrSize));
/* Disable the selected I2Cx Peripheral */
LL_I2C_Disable(I2Cx);
/*---------------------------- I2Cx CR1 Configuration ------------------------
* Configure the analog and digital noise filters with parameters :
* - AnalogFilter: I2C_CR1_ANFOFF bit
* - DigitalFilter: I2C_CR1_DNF[3:0] bits
*/
LL_I2C_ConfigFilters(I2Cx, I2C_InitStruct->AnalogFilter, I2C_InitStruct->DigitalFilter);
/*---------------------------- I2Cx TIMINGR Configuration --------------------
* Configure the SDA setup, hold time and the SCL high, low period with parameter :
* - Timing: I2C_TIMINGR_PRESC[3:0], I2C_TIMINGR_SCLDEL[3:0], I2C_TIMINGR_SDADEL[3:0],
* I2C_TIMINGR_SCLH[7:0] and I2C_TIMINGR_SCLL[7:0] bits
*/
LL_I2C_SetTiming(I2Cx, I2C_InitStruct->Timing);
/* Enable the selected I2Cx Peripheral */
LL_I2C_Enable(I2Cx);
/*---------------------------- I2Cx OAR1 Configuration -----------------------
* Disable, Configure and Enable I2Cx device own address 1 with parameters :
* - OwnAddress1: I2C_OAR1_OA1[9:0] bits
* - OwnAddrSize: I2C_OAR1_OA1MODE bit
*/
LL_I2C_DisableOwnAddress1(I2Cx);
LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
LL_I2C_EnableOwnAddress1(I2Cx);
/*---------------------------- I2Cx MODE Configuration -----------------------
* Configure I2Cx peripheral mode with parameter :
* - PeripheralMode: I2C_CR1_SMBDEN and I2C_CR1_SMBHEN bits
*/
LL_I2C_SetMode(I2Cx, I2C_InitStruct->PeripheralMode);
/*---------------------------- I2Cx CR2 Configuration ------------------------
* Configure the ACKnowledge or Non ACKnowledge condition
* after the address receive match code or next received byte with parameter :
* - TypeAcknowledge: I2C_CR2_NACK bit
*/
LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge);
return SUCCESS;
}
/**
* @brief Set each @ref LL_I2C_InitTypeDef field to default value.
* @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure.
* @retval None
*/
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct)
{
/* Set I2C_InitStruct fields to default values */
I2C_InitStruct->PeripheralMode = LL_I2C_MODE_I2C;
I2C_InitStruct->Timing = 0U;
I2C_InitStruct->AnalogFilter = LL_I2C_ANALOGFILTER_ENABLE;
I2C_InitStruct->DigitalFilter = 0U;
I2C_InitStruct->OwnAddress1 = 0U;
I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK;
I2C_InitStruct->OwnAddrSize = LL_I2C_OWNADDRESS1_7BIT;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_lptim.c
Executable
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/**
******************************************************************************
* @file stm32f7xx_ll_lptim.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief LPTIM LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_lptim.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (LPTIM1) || defined (LPTIM2)
/** @addtogroup LPTIM_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup LPTIM_LL_Private_Macros
* @{
*/
#define IS_LPTIM_CLOCK_SOURCE(__VALUE__) (((__VALUE__) == LL_LPTIM_CLK_SOURCE_INTERNAL) \
|| ((__VALUE__) == LL_LPTIM_CLK_SOURCE_EXTERNAL))
#define IS_LPTIM_CLOCK_PRESCALER(__VALUE__) (((__VALUE__) == LL_LPTIM_PRESCALER_DIV1) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV2) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV4) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV8) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV16) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV32) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV64) \
|| ((__VALUE__) == LL_LPTIM_PRESCALER_DIV128))
#define IS_LPTIM_WAVEFORM(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_PWM) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_WAVEFORM_SETONCE))
#define IS_LPTIM_OUTPUT_POLARITY(__VALUE__) (((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_REGULAR) \
|| ((__VALUE__) == LL_LPTIM_OUTPUT_POLARITY_INVERSE))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LPTIM_LL_Exported_Functions
* @{
*/
/** @addtogroup LPTIM_LL_EF_Init
* @{
*/
/**
* @brief Set LPTIMx registers to their reset values.
* @param LPTIMx LP Timer instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: LPTIMx registers are de-initialized
* - ERROR: invalid LPTIMx instance
*/
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef* LPTIMx)
{
ErrorStatus result = SUCCESS;
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
if (LPTIMx == LPTIM1)
{
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
}
#if defined(LPTIM2)
else if (LPTIMx == LPTIM2)
{
LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LPTIM2);
LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LPTIM2);
}
#endif
else
{
result = ERROR;
}
return result;
}
/**
* @brief Set each fields of the LPTIM_InitStruct structure to its default
* value.
* @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
* @retval None
*/
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
{
/* Set the default configuration */
LPTIM_InitStruct->ClockSource = LL_LPTIM_CLK_SOURCE_INTERNAL;
LPTIM_InitStruct->Prescaler = LL_LPTIM_PRESCALER_DIV1;
LPTIM_InitStruct->Waveform = LL_LPTIM_OUTPUT_WAVEFORM_PWM;
LPTIM_InitStruct->Polarity = LL_LPTIM_OUTPUT_POLARITY_REGULAR;
}
/**
* @brief Configure the LPTIMx peripheral according to the specified parameters.
* @note LL_LPTIM_Init can only be called when the LPTIM instance is disabled.
* @note LPTIMx can be disabled using unitary function @ref LL_LPTIM_Disable().
* @param LPTIMx LP Timer Instance
* @param LPTIM_InitStruct pointer to a @ref LL_LPTIM_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: LPTIMx instance has been initialized
* - ERROR: LPTIMx instance hasn't been initialized
*/
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef * LPTIMx, LL_LPTIM_InitTypeDef* LPTIM_InitStruct)
{
ErrorStatus result = SUCCESS;
/* The LPTIMx_CFGR register must only be modified when the LPTIM is disabled
(ENABLE bit is reset to 0).
*/
if (LL_LPTIM_IsEnabled(LPTIMx))
{
result = ERROR;
}
else
{
/* Check the parameters */
assert_param(IS_LPTIM_INSTANCE(LPTIMx));
assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->ClockSource));
assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler));
assert_param(IS_LPTIM_WAVEFORM(LPTIM_InitStruct->Waveform));
assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->Polarity));
/* Set CKSEL bitfield according to ClockSource value */
/* Set PRESC bitfield according to Prescaler value */
/* Set WAVE bitfield according to Waveform value */
/* Set WAVEPOL bitfield according to Polarity value */
MODIFY_REG(LPTIMx->CFGR,
(LPTIM_CFGR_CKSEL | LPTIM_CFGR_PRESC | LPTIM_CFGR_WAVE| LPTIM_CFGR_WAVPOL),
LPTIM_InitStruct->ClockSource | \
LPTIM_InitStruct->Prescaler | \
LPTIM_InitStruct->Waveform | \
LPTIM_InitStruct->Polarity);
}
return result;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (LPTIM1) || defined (LPTIM2) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_pwr.c
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/**
******************************************************************************
* @file stm32f7xx_ll_pwr.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief PWR LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_pwr.h"
#include "stm32f7xx_ll_bus.h"
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_LL_Exported_Functions
* @{
*/
/** @addtogroup PWR_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the PWR registers to their default reset values.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PWR registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_PWR_DeInit(void)
{
/* Force reset of PWR clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_PWR);
/* Release reset of PWR clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_PWR);
WRITE_REG(PWR->CR2, (PWR_CR2_CWUPF1 | PWR_CR2_CWUPF2 | PWR_CR2_CWUPF3 | PWR_CR2_CWUPF4 | PWR_CR2_CWUPF5 | PWR_CR2_CWUPF6));
return SUCCESS;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rcc.c
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rng.c
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/**
******************************************************************************
* @file stm32f7xx_ll_rng.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief RNG LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_rng.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (RNG)
/** @addtogroup RNG_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RNG_LL_Exported_Functions
* @{
*/
/** @addtogroup RNG_LL_EF_Init
* @{
*/
/**
* @brief De-initialize RNG registers (Registers restored to their default values).
* @param RNGx RNG Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RNG registers are de-initialized
* - ERROR: not applicable
*/
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx)
{
/* Check the parameters */
assert_param(IS_RNG_ALL_INSTANCE(RNGx));
/* Enable RNG reset state */
LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG);
/* Release RNG from reset state */
LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG);
return (SUCCESS);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (RNG) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_rtc.c
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/**
******************************************************************************
* @file stm32f7xx_ll_rtc.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief RTC LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_rtc.h"
#include "stm32f7xx_ll_cortex.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined(RTC)
/** @addtogroup RTC_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup RTC_LL_Private_Constants
* @{
*/
/* Default values used for prescaler */
#define RTC_ASYNCH_PRESC_DEFAULT 0x0000007FU
#define RTC_SYNCH_PRESC_DEFAULT 0x000000FFU
/* Values used for timeout */
#define RTC_INITMODE_TIMEOUT 1000U /* 1s when tick set to 1ms */
#define RTC_SYNCHRO_TIMEOUT 1000U /* 1s when tick set to 1ms */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RTC_LL_Private_Macros
* @{
*/
#define IS_LL_RTC_HOURFORMAT(__VALUE__) (((__VALUE__) == LL_RTC_HOURFORMAT_24HOUR) \
|| ((__VALUE__) == LL_RTC_HOURFORMAT_AMPM))
#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FU)
#define IS_LL_RTC_SYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0x7FFFU)
#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \
|| ((__VALUE__) == LL_RTC_FORMAT_BCD))
#define IS_LL_RTC_TIME_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_TIME_FORMAT_AM_OR_24) \
|| ((__VALUE__) == LL_RTC_TIME_FORMAT_PM))
#define IS_LL_RTC_HOUR12(__HOUR__) (((__HOUR__) > 0U) && ((__HOUR__) <= 12U))
#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U)
#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U)
#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U)
#define IS_LL_RTC_WEEKDAY(__VALUE__) (((__VALUE__) == LL_RTC_WEEKDAY_MONDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_TUESDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_WEDNESDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_THURSDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_FRIDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \
|| ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY))
#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U))
#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \
|| ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \
|| ((__VALUE__) == LL_RTC_MONTH_MARCH) \
|| ((__VALUE__) == LL_RTC_MONTH_APRIL) \
|| ((__VALUE__) == LL_RTC_MONTH_MAY) \
|| ((__VALUE__) == LL_RTC_MONTH_JUNE) \
|| ((__VALUE__) == LL_RTC_MONTH_JULY) \
|| ((__VALUE__) == LL_RTC_MONTH_AUGUST) \
|| ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \
|| ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \
|| ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \
|| ((__VALUE__) == LL_RTC_MONTH_DECEMBER))
#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U)
#define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_HOURS) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_MINUTES) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_SECONDS) \
|| ((__VALUE__) == LL_RTC_ALMA_MASK_ALL))
#define IS_LL_RTC_ALMB_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMB_MASK_NONE) \
|| ((__VALUE__) == LL_RTC_ALMB_MASK_DATEWEEKDAY) \
|| ((__VALUE__) == LL_RTC_ALMB_MASK_HOURS) \
|| ((__VALUE__) == LL_RTC_ALMB_MASK_MINUTES) \
|| ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \
|| ((__VALUE__) == LL_RTC_ALMB_MASK_ALL))
#define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \
((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY))
#define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \
((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RTC_LL_Exported_Functions
* @{
*/
/** @addtogroup RTC_LL_EF_Init
* @{
*/
/**
* @brief De-Initializes the RTC registers to their default reset values.
* @note This function doesn't reset the RTC Clock source and RTC Backup Data
* registers.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC registers are de-initialized
* - ERROR: RTC registers are not de-initialized
*/
ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx)
{
ErrorStatus status = ERROR;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
/* Set Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
/* Reset TR, DR and CR registers */
LL_RTC_WriteReg(RTCx, TR, 0x00000000U);
#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT);
#endif /* RTC_WAKEUP_SUPPORT */
LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0));
/* Reset All CR bits except CR[2:0] */
#if defined(RTC_WAKEUP_SUPPORT)
LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL));
#else
LL_RTC_WriteReg(RTCx, CR, 0x00000000U);
#endif /* RTC_WAKEUP_SUPPORT */
LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT));
LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U);
LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U);
LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U);
LL_RTC_WriteReg(RTCx, CALR, 0x00000000U);
LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U);
LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U);
/* Reset ISR register and exit initialization mode */
LL_RTC_WriteReg(RTCx, ISR, 0x00000000U);
/* Reset Tamper and alternate functions configuration register */
LL_RTC_WriteReg(RTCx, TAMPCR, 0x00000000U);
/* Reset Option register */
LL_RTC_WriteReg(RTCx, OR, 0x00000000U);
/* Wait till the RTC RSF flag is set */
status = LL_RTC_WaitForSynchro(RTCx);
}
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
return status;
}
/**
* @brief Initializes the RTC registers according to the specified parameters
* in RTC_InitStruct.
* @param RTCx RTC Instance
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains
* the configuration information for the RTC peripheral.
* @note The RTC Prescaler register is write protected and can be written in
* initialization mode only.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC registers are initialized
* - ERROR: RTC registers are not initialized
*/
ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct)
{
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_HOURFORMAT(RTC_InitStruct->HourFormat));
assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler));
assert_param(IS_LL_RTC_SYNCH_PREDIV(RTC_InitStruct->SynchPrescaler));
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
/* Set Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
/* Set Hour Format */
LL_RTC_SetHourFormat(RTCx, RTC_InitStruct->HourFormat);
/* Configure Synchronous and Asynchronous prescaler factor */
LL_RTC_SetSynchPrescaler(RTCx, RTC_InitStruct->SynchPrescaler);
LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler);
/* Exit Initialization mode */
LL_RTC_DisableInitMode(RTCx);
status = SUCCESS;
}
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
return status;
}
/**
* @brief Set each @ref LL_RTC_InitTypeDef field to default value.
* @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct)
{
/* Set RTC_InitStruct fields to default values */
RTC_InitStruct->HourFormat = LL_RTC_HOURFORMAT_24HOUR;
RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT;
RTC_InitStruct->SynchPrescaler = RTC_SYNCH_PRESC_DEFAULT;
}
/**
* @brief Set the RTC current time.
* @param RTCx RTC Instance
* @param RTC_Format This parameter can be one of the following values:
* @arg @ref LL_RTC_FORMAT_BIN
* @arg @ref LL_RTC_FORMAT_BCD
* @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains
* the time configuration information for the RTC.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC Time register is configured
* - ERROR: RTC Time register is not configured
*/
ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct)
{
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
{
assert_param(IS_LL_RTC_HOUR12(RTC_TimeStruct->Hours));
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
}
else
{
RTC_TimeStruct->TimeFormat = 0x00U;
assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours));
}
assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes));
assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds));
}
else
{
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
{
assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_TimeStruct->TimeFormat));
}
else
{
RTC_TimeStruct->TimeFormat = 0x00U;
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)));
}
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)));
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)));
}
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
/* Set Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
/* Check the input parameters format */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, RTC_TimeStruct->Hours,
RTC_TimeStruct->Minutes, RTC_TimeStruct->Seconds);
}
else
{
LL_RTC_TIME_Config(RTCx, RTC_TimeStruct->TimeFormat, __LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Hours),
__LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Minutes),
__LL_RTC_CONVERT_BIN2BCD(RTC_TimeStruct->Seconds));
}
/* Exit Initialization mode */
LL_RTC_DisableInitMode(RTC);
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
{
status = LL_RTC_WaitForSynchro(RTCx);
}
else
{
status = SUCCESS;
}
}
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
return status;
}
/**
* @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec).
* @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct)
{
/* Time = 00h:00min:00sec */
RTC_TimeStruct->TimeFormat = LL_RTC_TIME_FORMAT_AM_OR_24;
RTC_TimeStruct->Hours = 0U;
RTC_TimeStruct->Minutes = 0U;
RTC_TimeStruct->Seconds = 0U;
}
/**
* @brief Set the RTC current date.
* @param RTCx RTC Instance
* @param RTC_Format This parameter can be one of the following values:
* @arg @ref LL_RTC_FORMAT_BIN
* @arg @ref LL_RTC_FORMAT_BCD
* @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
* the date configuration information for the RTC.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC Day register is configured
* - ERROR: RTC Day register is not configured
*/
ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct)
{
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U))
{
RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU;
}
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
assert_param(IS_LL_RTC_YEAR(RTC_DateStruct->Year));
assert_param(IS_LL_RTC_MONTH(RTC_DateStruct->Month));
assert_param(IS_LL_RTC_DAY(RTC_DateStruct->Day));
}
else
{
assert_param(IS_LL_RTC_YEAR(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Year)));
assert_param(IS_LL_RTC_MONTH(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Month)));
assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_DateStruct->Day)));
}
assert_param(IS_LL_RTC_WEEKDAY(RTC_DateStruct->WeekDay));
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
/* Set Initialization mode */
if (LL_RTC_EnterInitMode(RTCx) != ERROR)
{
/* Check the input parameters format */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, RTC_DateStruct->Day, RTC_DateStruct->Month, RTC_DateStruct->Year);
}
else
{
LL_RTC_DATE_Config(RTCx, RTC_DateStruct->WeekDay, __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Day),
__LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Month), __LL_RTC_CONVERT_BIN2BCD(RTC_DateStruct->Year));
}
/* Exit Initialization mode */
LL_RTC_DisableInitMode(RTC);
/* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U)
{
status = LL_RTC_WaitForSynchro(RTCx);
}
else
{
status = SUCCESS;
}
}
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
return status;
}
/**
* @brief Set each @ref LL_RTC_DateTypeDef field to default value (date = Monday, January 01 xx00)
* @param RTC_DateStruct pointer to a @ref LL_RTC_DateTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct)
{
/* Monday, January 01 xx00 */
RTC_DateStruct->WeekDay = LL_RTC_WEEKDAY_MONDAY;
RTC_DateStruct->Day = 1U;
RTC_DateStruct->Month = LL_RTC_MONTH_JANUARY;
RTC_DateStruct->Year = 0U;
}
/**
* @brief Set the RTC Alarm A.
* @note The Alarm register can only be written when the corresponding Alarm
* is disabled (Use @ref LL_RTC_ALMA_Disable function).
* @param RTCx RTC Instance
* @param RTC_Format This parameter can be one of the following values:
* @arg @ref LL_RTC_FORMAT_BIN
* @arg @ref LL_RTC_FORMAT_BCD
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
* contains the alarm configuration parameters.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ALARMA registers are configured
* - ERROR: ALARMA registers are not configured
*/
ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
{
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
assert_param(IS_LL_RTC_ALMA_MASK(RTC_AlarmStruct->AlarmMask));
assert_param(IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
{
assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
}
else
{
RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
}
assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
{
assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
}
else
{
assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
}
}
else
{
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
{
assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
}
else
{
RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
}
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
{
assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
}
else
{
assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
}
}
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
/* Select weekday selection */
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE)
{
/* Set the date for ALARM */
LL_RTC_ALMA_DisableWeekday(RTCx);
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
LL_RTC_ALMA_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
}
else
{
LL_RTC_ALMA_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
}
}
else
{
/* Set the week day for ALARM */
LL_RTC_ALMA_EnableWeekday(RTCx);
LL_RTC_ALMA_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
}
/* Configure the Alarm register */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
}
else
{
LL_RTC_ALMA_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
}
/* Set ALARM mask */
LL_RTC_ALMA_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
return SUCCESS;
}
/**
* @brief Set the RTC Alarm B.
* @note The Alarm register can only be written when the corresponding Alarm
* is disabled (@ref LL_RTC_ALMB_Disable function).
* @param RTCx RTC Instance
* @param RTC_Format This parameter can be one of the following values:
* @arg @ref LL_RTC_FORMAT_BIN
* @arg @ref LL_RTC_FORMAT_BCD
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that
* contains the alarm configuration parameters.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: ALARMB registers are configured
* - ERROR: ALARMB registers are not configured
*/
ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
{
/* Check the parameters */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
assert_param(IS_LL_RTC_FORMAT(RTC_Format));
assert_param(IS_LL_RTC_ALMB_MASK(RTC_AlarmStruct->AlarmMask));
assert_param(IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(RTC_AlarmStruct->AlarmDateWeekDaySel));
if (RTC_Format == LL_RTC_FORMAT_BIN)
{
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
{
assert_param(IS_LL_RTC_HOUR12(RTC_AlarmStruct->AlarmTime.Hours));
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
}
else
{
RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours));
}
assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes));
assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds));
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
{
assert_param(IS_LL_RTC_DAY(RTC_AlarmStruct->AlarmDateWeekDay));
}
else
{
assert_param(IS_LL_RTC_WEEKDAY(RTC_AlarmStruct->AlarmDateWeekDay));
}
}
else
{
if (LL_RTC_GetHourFormat(RTCx) != LL_RTC_HOURFORMAT_24HOUR)
{
assert_param(IS_LL_RTC_HOUR12(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
assert_param(IS_LL_RTC_TIME_FORMAT(RTC_AlarmStruct->AlarmTime.TimeFormat));
}
else
{
RTC_AlarmStruct->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)));
}
assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)));
assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)));
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
{
assert_param(IS_LL_RTC_DAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
}
else
{
assert_param(IS_LL_RTC_WEEKDAY(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmDateWeekDay)));
}
}
/* Disable the write protection for RTC registers */
LL_RTC_DisableWriteProtection(RTCx);
/* Select weekday selection */
if (RTC_AlarmStruct->AlarmDateWeekDaySel == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE)
{
/* Set the date for ALARM */
LL_RTC_ALMB_DisableWeekday(RTCx);
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
LL_RTC_ALMB_SetDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
}
else
{
LL_RTC_ALMB_SetDay(RTCx, __LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmDateWeekDay));
}
}
else
{
/* Set the week day for ALARM */
LL_RTC_ALMB_EnableWeekday(RTCx);
LL_RTC_ALMB_SetWeekDay(RTCx, RTC_AlarmStruct->AlarmDateWeekDay);
}
/* Configure the Alarm register */
if (RTC_Format != LL_RTC_FORMAT_BIN)
{
LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat, RTC_AlarmStruct->AlarmTime.Hours,
RTC_AlarmStruct->AlarmTime.Minutes, RTC_AlarmStruct->AlarmTime.Seconds);
}
else
{
LL_RTC_ALMB_ConfigTime(RTCx, RTC_AlarmStruct->AlarmTime.TimeFormat,
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Hours),
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Minutes),
__LL_RTC_CONVERT_BIN2BCD(RTC_AlarmStruct->AlarmTime.Seconds));
}
/* Set ALARM mask */
LL_RTC_ALMB_SetMask(RTCx, RTC_AlarmStruct->AlarmMask);
/* Enable the write protection for RTC registers */
LL_RTC_EnableWriteProtection(RTCx);
return SUCCESS;
}
/**
* @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
* Day = 1st day of the month/Mask = all fields are masked).
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
{
/* Alarm Time Settings : Time = 00h:00mn:00sec */
RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMA_TIME_FORMAT_AM;
RTC_AlarmStruct->AlarmTime.Hours = 0U;
RTC_AlarmStruct->AlarmTime.Minutes = 0U;
RTC_AlarmStruct->AlarmTime.Seconds = 0U;
/* Alarm Day Settings : Day = 1st day of the month */
RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMA_DATEWEEKDAYSEL_DATE;
RTC_AlarmStruct->AlarmDateWeekDay = 1U;
/* Alarm Masks Settings : Mask = all fields are not masked */
RTC_AlarmStruct->AlarmMask = LL_RTC_ALMA_MASK_NONE;
}
/**
* @brief Set each @ref LL_RTC_AlarmTypeDef of ALARMA field to default value (Time = 00h:00mn:00sec /
* Day = 1st day of the month/Mask = all fields are masked).
* @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized.
* @retval None
*/
void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct)
{
/* Alarm Time Settings : Time = 00h:00mn:00sec */
RTC_AlarmStruct->AlarmTime.TimeFormat = LL_RTC_ALMB_TIME_FORMAT_AM;
RTC_AlarmStruct->AlarmTime.Hours = 0U;
RTC_AlarmStruct->AlarmTime.Minutes = 0U;
RTC_AlarmStruct->AlarmTime.Seconds = 0U;
/* Alarm Day Settings : Day = 1st day of the month */
RTC_AlarmStruct->AlarmDateWeekDaySel = LL_RTC_ALMB_DATEWEEKDAYSEL_DATE;
RTC_AlarmStruct->AlarmDateWeekDay = 1U;
/* Alarm Masks Settings : Mask = all fields are not masked */
RTC_AlarmStruct->AlarmMask = LL_RTC_ALMB_MASK_NONE;
}
/**
* @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* @ref LL_RTC_DisableWriteProtection before calling this function.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC is in Init mode
* - ERROR: RTC is not in Init mode
*/
ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx)
{
__IO uint32_t timeout = RTC_INITMODE_TIMEOUT;
ErrorStatus status = SUCCESS;
uint32_t tmp = 0U;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Check if the Initialization mode is set */
if (LL_RTC_IsActiveFlag_INIT(RTCx) == 0U)
{
/* Set the Initialization mode */
LL_RTC_EnableInitMode(RTCx);
/* Wait till RTC is in INIT state and if Time out is reached exit */
tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
while ((timeout != 0U) && (tmp != 1U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
timeout --;
}
tmp = LL_RTC_IsActiveFlag_INIT(RTCx);
if (timeout == 0U)
{
status = ERROR;
}
}
}
return status;
}
/**
* @brief Exit the RTC Initialization mode.
* @note When the initialization sequence is complete, the calendar restarts
* counting after 4 RTCCLK cycles.
* @note The RTC Initialization mode is write protected, use the
* @ref LL_RTC_DisableWriteProtection before calling this function.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC exited from in Init mode
* - ERROR: Not applicable
*/
ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx)
{
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Disable initialization mode */
LL_RTC_DisableInitMode(RTCx);
return SUCCESS;
}
/**
* @brief Waits until the RTC Time and Day registers (RTC_TR and RTC_DR) are
* synchronized with RTC APB clock.
* @note The RTC Resynchronization mode is write protected, use the
* @ref LL_RTC_DisableWriteProtection before calling this function.
* @note To read the calendar through the shadow registers after Calendar
* initialization, calendar update or after wakeup from low power modes
* the software must first clear the RSF flag.
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
* @param RTCx RTC Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: RTC registers are synchronised
* - ERROR: RTC registers are not synchronised
*/
ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx)
{
__IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT;
ErrorStatus status = SUCCESS;
uint32_t tmp = 0U;
/* Check the parameter */
assert_param(IS_RTC_ALL_INSTANCE(RTCx));
/* Clear RSF flag */
LL_RTC_ClearFlag_RS(RTCx);
/* Wait the registers to be synchronised */
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
while ((timeout != 0U) && (tmp != 0U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
timeout--;
}
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
if (timeout == 0U)
{
status = ERROR;
}
}
if (status != ERROR)
{
timeout = RTC_SYNCHRO_TIMEOUT;
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
while ((timeout != 0U) && (tmp != 1U))
{
if (LL_SYSTICK_IsActiveCounterFlag() == 1U)
{
timeout--;
}
tmp = LL_RTC_IsActiveFlag_RS(RTCx);
if (timeout == 0U)
{
status = ERROR;
}
}
}
return (status);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RTC) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_sdmmc.c
Executable
+1504
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_spi.c
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@@ -0,0 +1,589 @@
/**
******************************************************************************
* @file stm32f7xx_ll_spi.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief SPI LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_spi.h"
#include "stm32f7xx_ll_bus.h"
#include "stm32f7xx_ll_rcc.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
/** @addtogroup SPI_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SPI_LL_Private_Constants SPI Private Constants
* @{
*/
/* SPI registers Masks */
#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_CRCL | \
SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
SPI_CR1_BIDIMODE)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_LL_Private_Macros SPI Private Macros
* @{
*/
#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
|| ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
|| ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
|| ((__VALUE__) == LL_SPI_MODE_SLAVE))
#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_4BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_5BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_6BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_7BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_9BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_10BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_11BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_12BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_13BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_14BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_15BIT) \
|| ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
|| ((__VALUE__) == LL_SPI_POLARITY_HIGH))
#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
|| ((__VALUE__) == LL_SPI_PHASE_2EDGE))
#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
|| ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
|| ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
|| ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
|| ((__VALUE__) == LL_SPI_MSB_FIRST))
#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
|| ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_LL_Exported_Functions
* @{
*/
/** @addtogroup SPI_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the SPI registers to their default reset values.
* @param SPIx SPI Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx)
{
ErrorStatus status = ERROR;
/* Check the parameters */
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
#if defined(SPI1)
if (SPIx == SPI1)
{
/* Force reset of SPI clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
status = SUCCESS;
}
#endif /* SPI1 */
#if defined(SPI2)
if (SPIx == SPI2)
{
/* Force reset of SPI clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
/* Release reset of SPI clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
status = SUCCESS;
}
#endif /* SPI2 */
#if defined(SPI3)
if (SPIx == SPI3)
{
/* Force reset of SPI clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
/* Release reset of SPI clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
status = SUCCESS;
}
#endif /* SPI3 */
#if defined(SPI4)
if (SPIx == SPI4)
{
/* Force reset of SPI clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
status = SUCCESS;
}
#endif /* SPI4 */
#if defined(SPI5)
if (SPIx == SPI5)
{
/* Force reset of SPI clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
status = SUCCESS;
}
#endif /* SPI5 */
#if defined(SPI6)
if (SPIx == SPI6)
{
/* Force reset of SPI clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
/* Release reset of SPI clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
status = SUCCESS;
}
#endif /* SPI6 */
return status;
}
/**
* @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* @retval An ErrorStatus enumeration value. (Return always SUCCESS)
*/
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
{
ErrorStatus status = ERROR;
/* Check the SPI Instance SPIx*/
assert_param(IS_SPI_ALL_INSTANCE(SPIx));
/* Check the SPI parameters from SPI_InitStruct*/
assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
{
/*---------------------------- SPIx CR1 Configuration ------------------------
* Configure SPIx CR1 with parameters:
* - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
* - Master/Slave Mode: SPI_CR1_MSTR bit
* - ClockPolarity: SPI_CR1_CPOL bit
* - ClockPhase: SPI_CR1_CPHA bit
* - NSS management: SPI_CR1_SSM bit
* - BaudRate prescaler: SPI_CR1_BR[2:0] bits
* - BitOrder: SPI_CR1_LSBFIRST bit
* - CRCCalculation: SPI_CR1_CRCEN bit
*/
MODIFY_REG(SPIx->CR1,
SPI_CR1_CLEAR_MASK,
SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode |
SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
/*---------------------------- SPIx CR2 Configuration ------------------------
* Configure SPIx CR2 with parameters:
* - DataWidth: DS[3:0] bits
* - NSS management: SSOE bit
*/
MODIFY_REG(SPIx->CR2,
SPI_CR2_DS | SPI_CR2_SSOE,
SPI_InitStruct->DataWidth | (SPI_InitStruct->NSS >> 16U));
/*---------------------------- SPIx CRCPR Configuration ----------------------
* Configure SPIx CRCPR with parameters:
* - CRCPoly: CRCPOLY[15:0] bits
*/
if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
}
status = SUCCESS;
}
/* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
return status;
}
/**
* @brief Set each @ref LL_SPI_InitTypeDef field to default value.
* @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
{
/* Set SPI_InitStruct fields to default values */
SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
SPI_InitStruct->CRCPoly = 7U;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/** @addtogroup I2S_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2S_LL_Private_Constants I2S Private Constants
* @{
*/
/* I2S registers Masks */
#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
#define I2S_I2SPR_CLEAR_MASK 0x0002U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_LL_Private_Macros I2S Private Macros
* @{
*/
#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
|| ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
|| ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
|| ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
|| ((__VALUE__) == LL_I2S_POLARITY_HIGH))
#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
|| ((__VALUE__) == LL_I2S_STANDARD_MSB) \
|| ((__VALUE__) == LL_I2S_STANDARD_LSB) \
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
|| ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
|| ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
|| ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
|| ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
|| ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
&& ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
|| ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
|| ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_LL_Exported_Functions
* @{
*/
/** @addtogroup I2S_LL_EF_Init
* @{
*/
/**
* @brief De-initialize the SPI/I2S registers to their default reset values.
* @param SPIx SPI Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: SPI registers are de-initialized
* - ERROR: SPI registers are not de-initialized
*/
ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx)
{
return LL_SPI_DeInit(SPIx);
}
/**
* @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct.
* @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0),
* SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param SPIx SPI Instance
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* @retval An ErrorStatus enumeration value:
* - SUCCESS: SPI registers are Initialized
* - ERROR: SPI registers are not Initialized
*/
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
{
uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U;
uint32_t tmp = 0U;
uint32_t sourceclock = 0U;
ErrorStatus status = ERROR;
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
{
/*---------------------------- SPIx I2SCFGR Configuration --------------------
* Configure SPIx I2SCFGR with parameters:
* - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
* - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
* - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
* - ClockPolarity: SPI_I2SCFGR_CKPOL bit
*/
/* Write to SPIx I2SCFGR */
MODIFY_REG(SPIx->I2SCFGR,
I2S_I2SCFGR_CLEAR_MASK,
I2S_InitStruct->Mode | I2S_InitStruct->Standard |
I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
SPI_I2SCFGR_I2SMOD);
/*---------------------------- SPIx I2SPR Configuration ----------------------
* Configure SPIx I2SPR with parameters:
* - MCLKOutput: SPI_I2SPR_MCKOE bit
* - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
*/
/* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
* else, default values are used: i2sodd = 0U, i2sdiv = 2U.
*/
if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
{
/* Check the frame length (For the Prescaler computing)
* Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
*/
if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
{
/* Packet length is 32 bits */
packetlength = 2U;
}
/* If an external I2S clock has to be used, the specific define should be set
in the project configuration or in the stm32f7xx_ll_rcc.h file */
/* Get the I2S source clock value */
sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
/* Compute the Real divider depending on the MCLK output state with a floating point */
if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
{
/* MCLK output is enabled */
tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
else
{
/* MCLK output is disabled */
tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
}
/* Remove the floating point */
tmp = tmp / 10U;
/* Check the parity of the divider */
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U);
/* Compute the i2sdiv prescaler */
i2sdiv = (uint16_t)((tmp - i2sodd) / 2U);
/* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
i2sodd = (uint16_t)(i2sodd << 8U);
}
/* Test if the divider is 1 or 0 or greater than 0xFF */
if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
{
/* Set the default values */
i2sdiv = 2U;
i2sodd = 0U;
}
/* Write to SPIx I2SPR register the computed value */
WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
status = SUCCESS;
}
return status;
}
/**
* @brief Set each @ref LL_I2S_InitTypeDef field to default value.
* @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
{
/*--------------- Reset I2S init structure parameters values -----------------*/
I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
}
/**
* @brief Set linear and parity prescaler.
* @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n
* Check Audio frequency table and formulas inside Reference Manual (SPI/I2S).
* @param SPIx SPI Instance
* @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF.
* @param PrescalerParity This parameter can be one of the following values:
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
* @retval None
*/
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
{
/* Check the I2S parameters */
assert_param(IS_I2S_ALL_INSTANCE(SPIx));
assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
/* Write to SPIx I2SPR */
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c
Executable
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usart.c
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/**
******************************************************************************
* @file stm32f7xx_ll_usart.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief USART LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#if defined(USE_FULL_LL_DRIVER)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_usart.h"
#include "stm32f7xx_ll_rcc.h"
#include "stm32f7xx_ll_bus.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8)
/** @addtogroup USART_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup USART_LL_Private_Macros
* @{
*/
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
* divided by the smallest oversampling used on the USART (i.e. 8) */
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U)
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \
&& ((__VALUE__) <= 0x0000FFFFU))
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX) \
|| ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
|| ((__VALUE__) == LL_USART_PARITY_EVEN) \
|| ((__VALUE__) == LL_USART_PARITY_ODD))
#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_7B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_8B) \
|| ((__VALUE__) == LL_USART_DATAWIDTH_9B))
#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
|| ((__VALUE__) == LL_USART_OVERSAMPLING_8))
#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
|| ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
|| ((__VALUE__) == LL_USART_PHASE_2EDGE))
#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
|| ((__VALUE__) == LL_USART_POLARITY_HIGH))
#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
|| ((__VALUE__) == LL_USART_CLOCK_ENABLE))
#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_1) \
|| ((__VALUE__) == LL_USART_STOPBITS_1_5) \
|| ((__VALUE__) == LL_USART_STOPBITS_2))
#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
|| ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_LL_Exported_Functions
* @{
*/
/** @addtogroup USART_LL_EF_Init
* @{
*/
/**
* @brief De-initialize USART registers (Registers restored to their default values).
* @param USARTx USART Instance
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are de-initialized
* - ERROR: USART registers are not de-initialized
*/
ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
{
ErrorStatus status = SUCCESS;
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
if (USARTx == USART1)
{
/* Force reset of USART clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
/* Release reset of USART clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
}
else if (USARTx == USART2)
{
/* Force reset of USART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
}
else if (USARTx == USART3)
{
/* Force reset of USART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
/* Release reset of USART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
}
else if (USARTx == USART6)
{
/* Force reset of USART clock */
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
/* Release reset of USART clock */
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
}
else if (USARTx == UART4)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
}
else if (USARTx == UART5)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
}
else if (USARTx == UART7)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
}
else if (USARTx == UART8)
{
/* Force reset of UART clock */
LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
/* Release reset of UART clock */
LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
}
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Initialize USART registers according to the specified
* parameters in USART_InitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
* @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
{
ErrorStatus status = ERROR;
uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
/* Check the parameters */
assert_param(IS_UART_INSTANCE(USARTx));
assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
/* USART needs to be in disabled state, in order to be able to configure some bits in
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
/*---------------------------- USART CR1 Configuration ---------------------
* Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
* - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
* - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
* - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
* - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
*/
MODIFY_REG(USARTx->CR1,
(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
(USART_InitStruct->DataWidth | USART_InitStruct->Parity |
USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
/*---------------------------- USART CR2 Configuration ---------------------
* Configure USARTx CR2 (Stop bits) with parameters:
* - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
* - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
*/
LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
/*---------------------------- USART CR3 Configuration ---------------------
* Configure USARTx CR3 (Hardware Flow Control) with parameters:
* - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
*/
LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
/*---------------------------- USART BRR Configuration ---------------------
* Retrieve Clock frequency used for USART Peripheral
*/
if (USARTx == USART1)
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART1_CLKSOURCE);
}
else if (USARTx == USART2)
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART2_CLKSOURCE);
}
else if (USARTx == USART3)
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART3_CLKSOURCE);
}
else if (USARTx == USART6)
{
periphclk = LL_RCC_GetUSARTClockFreq(LL_RCC_USART6_CLKSOURCE);
}
else if (USARTx == UART4)
{
periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
}
else if (USARTx == UART5)
{
periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART5_CLKSOURCE);
}
else if (USARTx == UART7)
{
periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART7_CLKSOURCE);
}
else if (USARTx == UART8)
{
periphclk = LL_RCC_GetUARTClockFreq(LL_RCC_UART8_CLKSOURCE);
}
else
{
/* Nothing to do, as error code is already assigned to ERROR value */
}
/* Configure the USART Baud Rate :
- valid baud rate value (different from 0) is required
- Peripheral clock as returned by RCC service, should be valid (different from 0).
*/
if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
&& (USART_InitStruct->BaudRate != 0U))
{
status = SUCCESS;
LL_USART_SetBaudRate(USARTx,
periphclk,
USART_InitStruct->OverSampling,
USART_InitStruct->BaudRate);
/* Check BRR is greater than or equal to 16d */
assert_param(IS_LL_USART_BRR(USARTx->BRR));
}
}
/* Endif (=> USART not in Disabled state => return ERROR) */
return (status);
}
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
* @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
{
/* Set USART_InitStruct fields to default values */
USART_InitStruct->BaudRate = 9600U;
USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
}
/**
* @brief Initialize USART Clock related settings according to the
* specified parameters in the USART_ClockInitStruct.
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
* @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
* - ERROR: Problem occurred during USART Registers initialization
*/
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
ErrorStatus status = SUCCESS;
/* Check USART Instance and Clock signal output parameters */
assert_param(IS_UART_INSTANCE(USARTx));
assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
/* USART needs to be in disabled state, in order to be able to configure some bits in
CRx registers */
if (LL_USART_IsEnabled(USARTx) == 0U)
{
/*---------------------------- USART CR2 Configuration -----------------------*/
/* If Clock signal has to be output */
if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
{
/* Deactivate Clock signal delivery :
* - Disable Clock Output: USART_CR2_CLKEN cleared
*/
LL_USART_DisableSCLKOutput(USARTx);
}
else
{
/* Ensure USART instance is USART capable */
assert_param(IS_USART_INSTANCE(USARTx));
/* Check clock related parameters */
assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
/*---------------------------- USART CR2 Configuration -----------------------
* Configure USARTx CR2 (Clock signal related bits) with parameters:
* - Enable Clock Output: USART_CR2_CLKEN set
* - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
* - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
* - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
*/
MODIFY_REG(USARTx->CR2,
USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
}
}
/* Else (USART not in Disabled state => return ERROR */
else
{
status = ERROR;
}
return (status);
}
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
* @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
{
/* Set LL_USART_ClockInitStruct fields with default values */
USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_usb.c
Executable
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UHSDR-active-devel/mchf-eclipse/basesw/ovi40/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_utils.c
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/**
******************************************************************************
* @file stm32f7xx_ll_utils.c
* @author MCD Application Team
* @version V1.2.0
* @date 30-December-2016
* @brief UTILS LL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_utils.h"
#include "stm32f7xx_ll_rcc.h"
#include "stm32f7xx_ll_system.h"
#include "stm32f7xx_ll_pwr.h"
#ifdef USE_FULL_ASSERT
#include "stm32_assert.h"
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F7xx_LL_Driver
* @{
*/
/** @addtogroup UTILS_LL
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Constants
* @{
*/
#define UTILS_MAX_FREQUENCY_SCALE1 216000000U /*!< Maximum frequency for system clock at power scale1, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE2 180000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
#define UTILS_MAX_FREQUENCY_SCALE3 144000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
/* Defines used for PLL range */
#define UTILS_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
#define UTILS_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
#define UTILS_PLLVCO_OUTPUT_MIN 100000000U /*!< Frequency min for PLLVCO output, in Hz */
#define UTILS_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
/* Defines used for HSE range */
#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
#define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
/* Defines used for FLASH latency according to HCLK Frequency */
#define UTILS_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
#define UTILS_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
#define UTILS_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
#define UTILS_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
#define UTILS_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
#define UTILS_SCALE1_LATENCY6_FREQ 180000000U /*!< HCLK frequency to set FLASH latency 6 in power scale 1 with over-drive mode */
#define UTILS_SCALE1_LATENCY7_FREQ 210000000U /*!< HCLK frequency to set FLASH latency 7 in power scale 1 with over-drive mode */
#define UTILS_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
#define UTILS_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
#define UTILS_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
#define UTILS_SCALE2_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
#define UTILS_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
#define UTILS_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
#define UTILS_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
#define UTILS_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
#define UTILS_SCALE3_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup UTILS_LL_Private_Macros
* @{
*/
#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
|| ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB1_DIV_16))
#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_2) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_4) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_8) \
|| ((__VALUE__) == LL_RCC_APB2_DIV_16))
#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
|| ((__VALUE__) == LL_RCC_PLLM_DIV_63))
#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((50 <= (__VALUE__)) && ((__VALUE__) <= 432))
#define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
|| ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
|| ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
|| ((__VALUE__) == LL_RCC_PLLP_DIV_8))
#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
|| ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
/**
* @}
*/
/* Private function prototypes -----------------------------------------------*/
/** @defgroup UTILS_LL_Private_Functions UTILS Private functions
* @{
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
static ErrorStatus UTILS_PLL_IsBusy(void);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UTILS_LL_Exported_Functions
* @{
*/
/** @addtogroup UTILS_LL_EF_DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source to have 1ms time base.
* @note When a RTOS is used, it is recommended to avoid changing the Systick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param HCLKFrequency HCLK frequency in Hz
* @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
* @retval None
*/
void LL_Init1msTick(uint32_t HCLKFrequency)
{
/* Use frequency provided in argument */
LL_InitTick(HCLKFrequency, 1000U);
}
/**
* @brief This function provides accurate delay (in milliseconds) based
* on SysTick counter flag
* @note When a RTOS is used, it is recommended to avoid using blocking delay
* and use rather osDelay service.
* @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
* will configure Systick to 1ms
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
void LL_mDelay(uint32_t Delay)
{
__IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
/* Add this code to indicate that local variable is not used */
((void)tmp);
/* Add a period to guaranty minimum wait */
if(Delay < LL_MAX_DELAY)
{
Delay++;
}
while (Delay)
{
if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
{
Delay--;
}
}
}
/**
* @}
*/
/** @addtogroup UTILS_EF_SYSTEM
* @brief System Configuration functions
*
@verbatim
===============================================================================
##### System Configuration functions #####
===============================================================================
[..]
System, AHB and APB buses clocks configuration
(+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 216000000 Hz.
@endverbatim
@internal
Depending on the device voltage range, the maximum frequency should be
adapted accordingly:
(++) +------------------------------------------------------------------------------------------------+
(++) | Wait states | HCLK clock frequency (MHz) |
(++) | |-------------------------------------------------------------------------------|
(++) | (Latency) | voltage range | voltage range | voltage range | voltage range |
(++) | | 2.7V - 3.6V | 2.4V - 2.7V | 2.1V - 2.7V | 1.8V - 2.1V |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |0WS(1CPU cycle) | 0 < HCLK <= 30 | 0 < HCLK <= 24 | 0 < HCLK <= 22 | 0 < HCLK <= 20 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |1WS(2CPU cycle) | 30 < HCLK <= 60 | 24 < HCLK <= 48 | 22 < HCLK <= 44 | 20 < HCLK <= 44 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |2WS(3CPU cycle) | 60 < HCLK <= 90 | 48 < HCLK <= 72 | 44 < HCLK <= 66 | 40 < HCLK <= 60 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |3WS(4CPU cycle) | 90 < HCLK <= 120 | 72 < HCLK <= 96 | 66 < HCLK <= 88 | 60 < HCLK <= 80 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |4WS(5CPU cycle) | 120 < HCLK <= 150 | 96 < HCLK <= 120 | 88 < HCLK <= 110 | 80 < HCLK <= 100 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |5WS(6CPU cycle) | 150 < HCLK <= 180 | 120 < HCLK <= 144 | 110 < HCLK <= 132 | 100 < HCLK <= 120 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |6WS(7CPU cycle) | 180 < HCLK <= 210 | 144 < HCLK <= 168 | 132 < HCLK <= 154 | 120 < HCLK <= 140 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |7WS(8CPU cycle) | 210 < HCLK <= 216 | 168 < HCLK <= 192 | 154 < HCLK <= 176 | 140 < HCLK <= 160 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |8WS(9CPU cycle) | -- | 192 < HCLK <= 216 | 176 < HCLK <= 198 | 160 < HCLK <= 180 |
(++) |----------------|-------------------|-------------------|-------------------|-------------------|
(++) |9WS(10CPU cycle)| -- | -- | 198 < HCLK <= 216 | -- |
(++) +------------------------------------------------------------------------------------------------+
@endinternal
* @{
*/
/**
* @brief This function sets directly SystemCoreClock CMSIS variable.
* @note Variable can be calculated also through SystemCoreClockUpdate function.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @retval None
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
{
/* HCLK clock frequency */
SystemCoreClock = HCLKFrequency;
}
/**
* @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz (PLLVCO_input = HSI frequency / PLLM)
* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLP: ensure that max frequency at 216000000 Hz is reach (PLLVCO_output / PLLP)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq = 0U;
/* Check if one of the PLL is enabled */
if(UTILS_PLL_IsBusy() == SUCCESS)
{
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
/* Enable HSI if not enabled */
if(LL_RCC_HSI_IsReady() != 1U)
{
LL_RCC_HSI_Enable();
while (LL_RCC_HSI_IsReady() != 1U)
{
/* Wait for HSI ready */
}
}
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
UTILS_PLLInitStruct->PLLP);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @brief This function configures system clock with HSE as clock source of the PLL
* @note The application need to ensure that PLL is disabled.
* @note Function is based on the following formula:
* - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLP)
* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.10 MHz (PLLVCO_input = HSE frequency / PLLM)
* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz (PLLVCO_output = PLLVCO_input * PLLN)
* - PLLP: ensure that max frequency at 216000000 Hz is reached (PLLVCO_output / PLLP)
* @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
* @param HSEBypass This parameter can be one of the following values:
* @arg @ref LL_UTILS_HSEBYPASS_ON
* @arg @ref LL_UTILS_HSEBYPASS_OFF
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Max frequency configuration done
* - ERROR: Max frequency configuration not done
*/
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t pllfreq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
/* Check if one of the PLL is enabled */
if(UTILS_PLL_IsBusy() == SUCCESS)
{
/* Calculate the new PLL output frequency */
pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
/* Enable HSE if not enabled */
if(LL_RCC_HSE_IsReady() != 1U)
{
/* Check if need to enable HSE bypass feature or not */
if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
{
LL_RCC_HSE_EnableBypass();
}
else
{
LL_RCC_HSE_DisableBypass();
}
/* Enable HSE */
LL_RCC_HSE_Enable();
while (LL_RCC_HSE_IsReady() != 1U)
{
/* Wait for HSE ready */
}
}
/* Configure PLL */
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
UTILS_PLLInitStruct->PLLP);
/* Enable PLL and switch system clock to PLL */
status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
}
else
{
/* Current PLL configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup UTILS_LL_Private_Functions
* @{
*/
/**
* @brief Update number of Flash wait states in line with new frequency and current
voltage range.
* @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
* @param HCLK_Frequency HCLK frequency
* @retval An ErrorStatus enumeration value:
* - SUCCESS: Latency has been modified
* - ERROR: Latency cannot be modified
*/
static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
{
ErrorStatus status = SUCCESS;
uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
/* Frequency cannot be equal to 0 */
if(HCLK_Frequency == 0U)
{
status = ERROR;
}
else
{
if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
{
if(LL_PWR_IsEnabledOverDriveMode() != 0U)
{
if(HCLK_Frequency > UTILS_SCALE1_LATENCY7_FREQ)
{
/* 210 < HCLK <= 216 => 7WS (8 CPU cycles) */
latency = LL_FLASH_LATENCY_7;
}
else /* (HCLK_Frequency > UTILS_SCALE1_LATENCY6_FREQ) */
{
/* 180 < HCLK <= 210 => 6WS (7 CPU cycles) */
latency = LL_FLASH_LATENCY_6;
}
}
if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ) && (latency == LL_FLASH_LATENCY_0))
{
/* 150 < HCLK <= 180 => 5WS (6 CPU cycles) */
latency = LL_FLASH_LATENCY_5;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ) && (latency == LL_FLASH_LATENCY_0))
{
/* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
latency = LL_FLASH_LATENCY_4;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ) && (latency == LL_FLASH_LATENCY_0))
{
/* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
latency = LL_FLASH_LATENCY_3;
}
else if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ) && (latency == LL_FLASH_LATENCY_0))
{
/* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ) && (latency == LL_FLASH_LATENCY_0))
{
/* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
/* else HCLK_Frequency < 30MHz default LL_FLASH_LATENCY_0 0WS */
}
}
else if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
{
if(HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)
{
/* 150 < HCLK <= 168 OR 150 < HCLK <= 180 (when OverDrive mode is enable) => 5WS (6 CPU cycles) */
latency = LL_FLASH_LATENCY_5;
}
else if(HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)
{
/* 120 < HCLK <= 150 => 4WS (5 CPU cycles) */
latency = LL_FLASH_LATENCY_4;
}
else if(HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)
{
/* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
latency = LL_FLASH_LATENCY_3;
}
else if(HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)
{
/* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if(HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)
{
/* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
/* else HCLK_Frequency < 24MHz default LL_FLASH_LATENCY_0 0WS */
}
}
else /* Scale 3 */
{
if(HCLK_Frequency > UTILS_SCALE3_LATENCY4_FREQ)
{
/* 120 < HCLK <= 144 => 4WS (5 CPU cycles) */
latency = LL_FLASH_LATENCY_4;
}
else if(HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)
{
/* 90 < HCLK <= 120 => 3WS (4 CPU cycles) */
latency = LL_FLASH_LATENCY_3;
}
else if(HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)
{
/* 60 < HCLK <= 90 => 2WS (3 CPU cycles) */
latency = LL_FLASH_LATENCY_2;
}
else
{
if(HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)
{
/* 30 < HCLK <= 60 => 1WS (2 CPU cycles) */
latency = LL_FLASH_LATENCY_1;
}
/* else HCLK_Frequency < 22MHz default LL_FLASH_LATENCY_0 0WS */
}
}
LL_FLASH_SetLatency(latency);
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(LL_FLASH_GetLatency() != latency)
{
status = ERROR;
}
}
return status;
}
/**
* @brief Function to check that PLL can be modified
* @param PLL_InputFrequency PLL input frequency (in Hz)
* @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
* the configuration information for the PLL.
* @retval PLL output frequency (in Hz)
*/
static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
{
uint32_t pllfreq = 0U;
/* Check the parameters */
assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
/* Check different PLL parameters according to RM */
/* - PLLM: ensure that the VCO input frequency ranges from 0.95 to 2.1 MHz. */
pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
/* - PLLN: ensure that the VCO output frequency is between 100 and 432 MHz.*/
pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
/* - PLLP: ensure that max frequency at 216000000 Hz is reached */
pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
return pllfreq;
}
/**
* @brief Function to check that PLL can be modified
* @retval An ErrorStatus enumeration value:
* - SUCCESS: PLL modification can be done
* - ERROR: PLL is busy
*/
static ErrorStatus UTILS_PLL_IsBusy(void)
{
ErrorStatus status = SUCCESS;
/* Check if PLL is busy*/
if(LL_RCC_PLL_IsReady() != 0U)
{
/* PLL configuration cannot be modified */
status = ERROR;
}
/* Check if PLLSAI is busy*/
if(LL_RCC_PLLSAI_IsReady() != 0U)
{
/* PLLSAI1 configuration cannot be modified */
status = ERROR;
}
/* Check if PLLI2S is busy*/
if(LL_RCC_PLLI2S_IsReady() != 0U)
{
/* PLLI2S configuration cannot be modified */
status = ERROR;
}
return status;
}
/**
* @brief Function to enable PLL and switch system clock to PLL
* @param SYSCLK_Frequency SYSCLK frequency
* @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
* the configuration information for the BUS prescalers.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: No problem to switch system to PLL
* - ERROR: Problem to switch system to PLL
*/
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
ErrorStatus status = SUCCESS;
uint32_t hclk_frequency = 0U;
assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
/* Calculate HCLK frequency */
hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
/* Increasing the number of wait states because of higher CPU frequency */
if(SystemCoreClock < hclk_frequency)
{
/* Set FLASH latency to highest latency */
status = UTILS_SetFlashLatency(hclk_frequency);
}
/* Update system clock configuration */
if(status == SUCCESS)
{
/* Enable PLL */
LL_RCC_PLL_Enable();
while (LL_RCC_PLL_IsReady() != 1U)
{
/* Wait for PLL ready */
}
/* Sysclk activation on the main PLL */
LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
{
/* Wait for system clock switch to PLL */
}
/* Set APB1 & APB2 prescaler*/
LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(SystemCoreClock > hclk_frequency)
{
/* Set FLASH latency to lowest latency */
status = UTILS_SetFlashLatency(hclk_frequency);
}
/* Update SystemCoreClock variable */
if(status == SUCCESS)
{
LL_SetSystemCoreClock(hclk_frequency);
}
return status;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/