153 lines
3.9 KiB
INI
153 lines
3.9 KiB
INI
# script for stm32h7x family
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#
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# stm32h7 devices support both JTAG and SWD transports.
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#
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source [find target/swj-dp.tcl]
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source [find mem_helper.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32h7x
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}
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set _ENDIAN little
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# Work-area is a space in RAM used for flash programming
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# By default use 64kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x10000
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}
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#jtag scan chain
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if { [info exists CPUTAPID] } {
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set _CPUTAPID $CPUTAPID
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} else {
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if { [using_jtag] } {
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set _CPUTAPID 0x6ba00477
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} {
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set _CPUTAPID 0x6ba02477
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}
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}
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swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID] } {
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set _BSTAPID1 $BSTAPID
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} else {
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# See STM Document RM0399
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# Section 40.6.1
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# STM32H74xxI
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set _BSTAPID1 0x06450041
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}
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1
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}
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
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# check for second flash bank
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if { [regexp -nocase {stm32h74..i..|stm32h75..i..} $_CHIPNAME] } {
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# STM32H7xxxI 2Mo have a dual bank flash.
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# Add the second flash bank.
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set _FLASHNAME $_CHIPNAME.flash1
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flash bank $_FLASHNAME stm32h7x 0x08100000 0 0 0 $_TARGETNAME
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}
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# Clock after reset is HSI at 64 MHz, no need of PLL
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if { [info exists CLOCK_FREQ] } {
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set _CLOCK_FREQ $CLOCK_FREQ
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} else {
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set _CLOCK_FREQ 1800
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}
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adapter_khz 1800
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adapter_nsrst_delay 100
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if {[using_jtag]} {
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jtag_ntrst_delay 100
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}
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if {![using_hla]} {
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m reset_config sysresetreq
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}
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$_TARGETNAME configure -event trace-config {
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# Set TRACE_CLKEN; TRACE_MODE is set to async; when using sync
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# change this value accordingly to configure trace pins
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# assignment
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mmw 0x5C001004 0x00100000 0
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}
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$_TARGETNAME configure -event reset-init {
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global ENABLE_LOW_POWER
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global STOP_WATCHDOG
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global _CLOCK_FREQ
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# Not done in target examine-end because device can be under reset and we get comm errors
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# Enable D3 and D1 DBG clocks
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# DBGMCU_CR |= DBG_CKEN_D3 | DBG_CKEN_D1
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mmw 0x5C001004 0x00600000 0
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if { [expr ($ENABLE_LOW_POWER == 1)] } {
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# Enable debug during low power modes (uses more power)
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# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
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mmw 0x5C001004 0x000001BF 0
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}
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if { [expr ($ENABLE_LOW_POWER == 0)] } {
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# Disable debug during low power modes
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# DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP)
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mmw 0x5C001004 0 0x000001BF
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}
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if { [expr ($STOP_WATCHDOG == 1)] } {
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# Stop watchdog counters during halt
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# DBGMCU_D1APB1_FZ |= DBG_WWDG1_STOP
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mmw 0x5C001034 0x00000040 0
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# DBGMCU_D2APB1_FZ |= DBG_WWDG2_STOP
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mmw 0x5C00103C 0x00000800 0
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# DBGMCU_D3APB1_FZ |= DBG_WDGLSD2_STOP | DBG_WDGLSD1_STOP
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mmw 0x5C001054 0x000C0000 0
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}
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if { [expr ($STOP_WATCHDOG == 0)] } {
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# Don't stop watchdog counters during halt
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# DBGMCU_D1APB1_FZ |= ~DBG_WWDG1_STOP
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mmw 0x5C001034 0 0x00000040
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# DBGMCU_D2APB1_FZ |= ~DBG_WWDG2_STOP
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mmw 0x5C00103C 0 0x00000800
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# DBGMCU_D3APB1_FZ |= ~(DBG_WDGLSD2_STOP | DBG_WDGLSD1_STOP)
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mmw 0x5C001054 0 0x000C0000
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}
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if { [expr ($ENABLE_LOW_POWER == 0)] && [expr ($STOP_WATCHDOG == 0)] } {
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# Disable D3 and D1 DBG clocks
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# DBGMCU_CR |= ~(DBG_CKEN_D3 | DBG_CKEN_D1)
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mmw 0x5C001004 0 0x00600000
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}
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# Clock after reset is HSI at 64 MHz, no need of PLL
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adapter_khz $_CLOCK_FREQ
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}
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$_TARGETNAME configure -event gdb-attach {
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global CONNECT_UNDER_RESET
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# Needed to be able to use the connect_assert_srst in reset_config
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# otherwise, can't read device flash size register
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if { [expr ($CONNECT_UNDER_RESET == 1)] } {
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reset init
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}
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}
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